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Электронный компонент: SY88149CLKG

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SY88149CL
3.3V, 1.25Gbps PECL Limiting Post
Amplifier w/High Gain TTL Signal Detect
November 2005
1
M9999-112205-A1
hbwhelp@micrel.com
or (408) 955-1690
General Description
The SY88149CL is a high-sensitivity limiting post
amplifier designed for use in fiber-optic receivers. These
devices connect to typical transimpedance amplifiers
(TIAs). The linear signal output from TIAs can contain
significant amounts of noise and may vary in amplitude
over time. The SY88149CL quantizes these signals and
outputs PECL level waveforms.
The SY88149CL operates from a single +3.3V power
supply, over temperatures ranging from 40
o
C to +85
o
C.
With its wide bandwidth and high gain, signals with data
rates up to 1.25Gbps, and as small as 5mV
pp
, can be
amplified to drive devices with PECL inputs.
The SY88149CL generates a high-gain signal-detect
(SD) open-collector TTL output. The SD function has a
high gain input stage for increased sensitivity. A
programmable Signal Detect level set pin (SD
LVL
) sets
the sensitivity of the input amplitude detection. SD
asserts high if the input amplitude rises above the
threshold set by SD
LVL
and de-asserts low otherwise.
The enable input (EN) de-asserts the true output signal
without removing the input signal. The SD output can be
fed back to the EN input to maintain output stability
under a loss-of-signal condition. Typically, 3.4dB SD
hysteresis is provided to prevent chattering.
All support documentation can be found on Micrel's web
site at:
www.micrel.com
.
Features
Single 3.3V power supply
Fast SD enable/disable time
622Mbps to 1.25Gbps operation
Low-noise PECL data outputs
High-gain SD
Chatter-free Open-Collector TTL signal detect (SD)
output with internal 4.75k
pull-up resistor
TTL EN input
Programmable SD level set (SD
LVL
)
Available in a tiny 10-pin MSOP package
Applications
GE-PON/GPON/EPON
Gigabit Ethernet
1062Mbps Fibre
Channel
OC-12/24 SONET/SDH
High-gain line driver and line receiver
Low-gain TIA interface
Markets
FTTH/FTTP
Datacom/Telecom
Optical transceiver







Micrel, Inc.
SY88149CL
November 2005
2
M9999-112205-A1
hbwhelp@micrel.com
or (408) 955-1690
Typical Application Circuit
Micrel, Inc.
SY88149CL
November 2005
3
M9999-112205-A1
hbwhelp@micrel.com
or (408) 955-1690
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead Finish
SY88149CLKG K10-1
Industrial
SY88149CL
with
Pb-Free bar line indicator
NiPdAu Pb-Free
SY88149CLKGTR
(1)
K10-1
Industrial
SY88149CL with Pb-Free bar line indicator
NiPdAu Pb-Free
Notes:
1. Tape
and
Reel.


Pin Configuration
10-Pin MSOP (K10-1)

Pin Description
Pin Number
Pin Name
Type
Pin Function
1 EN
TTL Input: Default is
HIGH.
Enable: This input enables the outputs when it is HIGH. Note
that this input is internally connected to a 25k pull-up resistor
and will default to a logic HIGH state if left open.
2
DIN
Data Input
True data input.
3
/DIN
Data Input
Complementary data input.
4 VREF
Reference voltage: Placing a capacitor here to V
CC
helps
stabilize SD
LVL
.
5 SDLVL
Input Signal Detect Level Set: a resistor from this pin to V
CC
sets the
threshold for the data input amplitude at which SD will be
asserted.
6 GND Ground
Device
ground.
7 SD
Open-collector TTL
output w/internal 4.75k
pull-up resistor
Signal-Detect asserts high when the data input amplitude rises
above the threshold set by SD
LVL
.
8
/DOUT
PECL Output
Complementary data output.
9
DOUT
PECL Output
True data output.
10
VCC
Power Supply
Positive power supply.

Micrel, Inc.
SY88149CL
November 2005
4
M9999-112205-A1
hbwhelp@micrel.com
or (408) 955-1690
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ....................................... 0V to +7.0V
Input Voltage (DIN, /DIN) .......................................0 to V
CC
Output Current (I
OUT
)
Continuous........................................................ 50mA
Surge ..............................................................100mA
EN Voltage .............................................................0 to V
CC
V
REF
Current .......................................... -800A to +500A
SD
LVL
Voltage ................................................... V
REF
to V
CC
Lead Temperature (soldering, 20sec.) ..................... 260C
Storage Temperature (T
s
) ....................... 65C to +150C
Operating Ratings
(2)
Supply Voltage (V
CC
)............................. +3.0V to +3.6V
Ambient Temperature (T
A
) ................... 40C to +85C
Junction Temperature (T
J
) ................. 40C to +120C
Junction Thermal Resistance
MSOP
(
JA
) Still-air ................................... 113C/W
DC Electrical Characteristics
V
CC
= 3.0 to 3.6V; R
L
= 50 to V
CC
-2V; T
A
= 40C to +85C, typical values at V
CC
= 3.3V, T
A
= 25C.
Symbol Parameter
Condition
Min
Typ Max Units
I
CC
Power Supply Current
No output load
26
39
mA
SD
LVL
SD
LVL
Voltage
V
REF
V
CC
V
V
OH
PECL Output HIGH Voltage
V
CC
-1.085 V
CC
-0.955 V
CC
-0.880
V
V
OL
PECL Output LOW Voltage
V
CC
-1.830 V
CC
-1.705 V
CC
-1.555
V
V
IHCMR
Common Mode Range
GND+2.0
V
CC
V
V
REF
Reference
Voltage
V
CC
-1.48 V
CC
-1.32 V
CC
-1.16
V
TTL DC Electrical Characteristics
V
CC
= 3.0 to 3.6V; R
L
= 50 to V
CC
-2V; T
A
= 40C to +85C, typical values at V
CC
= 3.3V, T
A
= 25C.
Symbol Parameter
Condition
Min
Typ Max Units
V
IH
EN Input HIGH Voltage
2.0
V
V
IL
EN Input LOW Voltage
0.8
V
I
IH
EN Input HIGH Current
V
IN
= 2.7V
V
IN
= V
CC
20
100
A
A
I
IL
EN Input LOW Current
V
IN
= 0.5V
-0.3
mA
V
OH
SD Output HIGH Level
V
CC
> 3.3V, I
OH-MAX
< 160A
V
CC
< 3.3V, I
OH-MAX
< 160A
2.4
2.0
V
V
V
OL
SD Output LOW Level
I
OL
= +2mA
0.5
V
Notes:
1.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3.
Thermal performance assumes the use of a 4-layer PCB. Exposed pad must be soldered (or equivalent) to the device's most negative potential
on the PCB
.
Micrel, Inc.
SY88149CL
November 2005
5
M9999-112205-A1
hbwhelp@micrel.com
or (408) 955-1690
AC Electrical Characteristics
V
CC
= 3.0V to 3.6V; R
LOAD
= 50
to V
CC
2V; T
A
= 40C to +85C.
Symbol Parameter
Condition
Min
Typ
Max
Units
t
r
, t
f
Output Rise/Fall Time
(20% to 80%)
Note 4
260
ps
t
JITTER
Deterministic
Random
Note 5
Note 6
15
5
ps
PP
ps
RMS
V
ID
Differential Input Voltage Swing
Figure 1
5
1800
mV
PP
V
OD
Differential Output Voltage
Swing
V
ID
> 18mV
PP
Figure 1
1500
mV
PP
T
OFF
SD Release Time
100
500
ns
T
ON
SD
Assert
Time
100
500
ns
SD
AL
Low SD Assert Level
R
SDLVL
= 15k
, Note 8
3.4
mV
PP
SD
DL
Low SD De-assert Level
R
SDLVL
= 15k
, Note 8
2.3 mV
PP
HYS
L
Low SD Hysteresis
R
SDLVL
= 15k
, Note 7
3.4 dB
SD
AM
Medium SD Assert Level
R
SDLVL
= 5k
, Note 8
6.2 8 mV
PP
SD
DM
Medium SD De-assert Level
R
SDLVL
= 5k
, Note 8
3 4.2 mV
PP
HYS
M
Medium SD Hysteresis
R
SDLVL
= 5k
, Note 7
2 3.4 5 dB
SD
AH
High SD Assert Level
R
SDLVL
= 100
, Note 8
16.4 20 mV
PP
SD
DH
High SD De-assert Level
R
SDLVL
= 100
, Note 8
8 10.8 mV
PP
HYS
H
High SD Hysteresis
R
SDLVL
= 100
, Note 7
2 3.4 5 dB
B
-3dB
3dB
Bandwidth
1
GHz
A
V(Diff)
Differential Voltage Gain
42
dB
S
21
Single-ended Small-Signal Gain
36
dB
Notes:
4. Amplifier in limiting mode. Input is a 200MHz square wave.
5. Deterministic jitter measured using 1.25Gbps K28.5 pattern, V
ID
= 10mV
PP
.
6. Random jitter measured using 1.25Gbps K28.7 pattern, V
ID
= 10mV
PP
.
7. This specification defines electrical hysteresis as 20log(SD Assert/SD De-assert). The ratio between optical hysteresis and
electrical hysteresis is found to vary between 1.5 and 2 depending upon the level of received optical power and ROSA
characteristics. Based upon that ratio, the optical hysteresis corresponding to the electrical hysteresis range 2dB-5dB, shown
in the AC characteristics table, will be 1dB-4dB optical Hysteresis.
8. See "Typical Operating Characteristics" for a graph showing how to choose a particular R
SDLVL
for a particular SD assert and
its associated de-assert amplitude.