SY87702L
1
Micrel, Inc.
M9999-102405
hbwhelp@micrel.com or (408) 955-1690
Rev.: C
Amendment: /0
Issue Date: October 2005
DESCRIPTION
FEATURES
SY87702L
s
3.3V power supply
s
Complies with Bellcore, ITU/CCITT and ANSI
specifications for applications such as OC-1, OC-3,
OC-12, OC-48*, and ATM
s
Compatible with FDDI, Gigabit Ethernet, Fibre
Channel, 2X Fibre Channel, SMPTE 259 and 292, and
proprietary applications
s
Low power
s
Clock and data recovery from 28Mbps up to 2.5Gbps
NRZ data stream
s
Selectable reference frequencies via programmable
multiplier
s
Differential PECL and CML high-speed serial outputs
s
Line receiver input: no external buffering needed
s
Link fault indication
s
100K ECL compatible I/O
s
Available in 64-Pin EP-TQFP package
The SY87702L is a complete Clock Recovery and Data
retiming integrated circuit for data rates from 28Mbps up to
2.5Gbps NRZ. The device is ideally suited for SONET/SDH/
ATM, Fibre Channel, and Gigabit Ethernet applications, as
well as other high-speed data transmission applications.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming data
stream. The VCO center frequency is controlled by the
reference clock frequency and the selected divide ratio. On-
chip clock generation is performed through the use of a
frequency multiplier PLL and can be used as a Clock
Multiplier Unit (CMU). The integrated CMU can provide this
clock signal at the TCLK outputs. Additionally, the TCLK
output can be selected to provide a copy of the RCLK
frequency.
For SONET/SDH applications, the SY87702L includes a
Link Fault Detection circuit. This circuit, enabled by the output
of an optical module driving the CD input low, causes the
recovery PLL of the SY87702L to lock to the reference
clock's multiplied frequency under Loss-of-Signal conditions.
This low jitter clock is provided at the RCLK outputs and is
at the same frequency as that provided at the TCLK output.
3.3V 28Mbps-2.5Gbps AnyRate
CLOCK AND DATA RECOVERY
APPLICATIONS
s
Transponders and section repeaters
s
Multiplexer's: access, add drop (ADM), and terminal
(TM)
s
SONET/SDH/ATM: -based transmission systems,
modules, and test equipment
s
Terabit routers and broadband cross-connects
s
Fibre optic test equipment
s
HDTV switching and transmission
*Meets OC-48 Jitter Tolerance and Transfer
AnyRate
is a registered trademark of Micrel, Inc.
SY87702L
2
Micrel, Inc.
M9999-102405
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
64-Pin EPAD TQFP (H63-1)
Ordering Information
(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY87702LHI
H64-1
Industrial
SY87702LHI
Sn-Pb
SY87702LHITR
(2)
H64-1
Industrial
SY87702LHI
Sn-Pb
SY87702LHG
(3)
H64-1
Industrial
SY87702LHG with
NiPdAu
Pb-Free bar line indicator Pb-Free
SY87702LHGTR
(2, 3)
H64-1
Industrial
SY87702LHG with
NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25
C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
1
64-Pin
EPAD-TQFP
2
3
4
5
6
7
8
9
10
11
12
13
17 18 19 20 21 22 23 24 25 26 27 28 29
48
47
46
45
44
43
42
41
40
39
38
37
36
61 60 59 58 57 56 55 54 53 52 51 50 49
VCOSEL1
PLLRN+
PLLRN
PLLRW+
NC
VCCA
PLLSW
PLLSW+
NC
PLLSN
NC
14
15
16
35
34
33
62
63
64
30 31 32
RDIN+
PLLRW
GNDA
PLLSN+
NC
NC
NC
VCC
REFCLK
REFCLK+
GND
VCC
GND
GND
NC
DIVSEL3
NC
CLKSEL
GND
DIVSEL1
DIVSEL2
NC
TCLKC
TCLKC+
TCLKE
TCLKE+
VCCO
RCLKC
RCLKC+
RCLKE
RCLKE+
VCCO
RDOUTC
RDOUTC+
RDOUTE
RDOUTE+
ENPECL
GND
RDIN
LFIN
NC
NC
VCCO
VCC
GND
GND
VCC
GND
CD
FREQSEL3
FREQSEL2
FREQSEL1
VCOSEL2
SY87702L
3
Micrel, Inc.
M9999-102405
hbwhelp@micrel.com or (408) 955-1690
Optical
Module
SY87702L
CDR/CMU
SY877XXL
Frame
Detector
Serial
EEPROM
Sel CD Lock
RX Data
Stream
TX Data Stream
Carrier Detect
Ref
Code Group Data
(4, 5, 8, 10, Bits)
Code Group Strobe
Code Group
Rate Clock
Alignment
Detect
Reference
Timing (8)
RX Data
RX Cloc
k
Align
SY877XXL
Mux/Demux
SY877XXL
Programmable
Protocol
Selector
Note:
Add second SY877XXL
for 16 or 20 bit parallel
input and output.
TXCLK
SYSTEM BLOCK DIAGRAM
SY87702L
4
Micrel, Inc.
M9999-102405
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL BLOCK DIAGRAM
RCLKE+
RCLKE
RCLKC+
RCLKC
LFIN
Link Fault
Detector
TCLKE+
TCLKE
TCLKC+
TCLKC
VCO
N/W1/W2/W3
Phase
Detector
Phase/
Frequency
Detector
NC*
PLLR
W
PLLR
W+
PLLRN
PLLRN+
VCO
N/W1/W2/W3
Phase/
Frequency
Detector
Charge
Pump
N/W
Divide by 1, 2,
4, 8, 10, 16,
20, 32
FREQSEL1
FREQSEL2
FREQSEL3
ENPECL
CD
RDIN+
RDIN
Charge
Pump
N/W
Mux
DIVSEL3
DIVSEL2
DIVSEL1
VCOSEL2
VCOSEL1
PLLSN+
PLLSN
PLLSW+
PLLSW
Mux
CLKSEL
RDOUTC+
RDOUTC
RDOUTE+
RDOUTE
REFCLK+
REFCLK
* Do not connect.
SY87702L
5
Micrel, Inc.
M9999-102405
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The clock is
phase aligned by a PLL so that it samples the data in the
center of the data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability, without incoming data, is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the multiplied frequency
of the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30
s data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
PIN NAMES
INPUTS
RDIN
[Serial Data Input] Differential PECL
This differential input accepts the receive serial data
stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN pin has an
internal 75K
resistor tied to V
CC
.
REFCLK
[Reference Clock] Differential PECL
This input is used as the reference for the internal
frequency synthesizer and the "training" frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 325MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK pin has an
internal 75K
resistor tied to V
CC
.
CD [Carrier Detect] PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW, the
data on the RDIN input will be internally forced to a constant
LOW, the data output RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW, and the clock
recovery PLL forced to lock onto the clock frequency
generated from REFCLK.
VCOSEL1, VCOSEL2 [VCO Select] TTL Inputs
These inputs select the VCO frequency range via either
one of three wide-band PLLs, or a SONET/SDH specific
narrow-band PLL. Only the selected PLL is enabled. All
other PLL's are disabled. Please refer to Table 1.
VCOSEL1
VCOSEL2
Choice
0
0
SONET/SDH
0
1
1.8 to 2.5GHz
1
0
1.25 to 1.8GHz
1
1
0.650 to 1.30GHz
Table. 1
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