PRELIMINARY
INFORMATION
SY69712A
5-628
DESCRIPTION
SYNERGY
SEMICONDUCTOR
FEATURES
PRELIMINARY
INFORMATION
SY69712A
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A complete SONET/SDH Transmitter and Receiver
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Complies with Bellcore, ITU/CCITT and ANSI
specifications
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Two on-chip PLLs: One for clock generation &
another for clock recovery
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SONET 622.08 Mbit/sec data rates (OC-12)
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Reference frequency of 19.44MHz, 51.84MHz or
77.76MHz
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Compatible with optic modules with and without
on-board clock recovery
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TTL/CMOS-compatible parallel I/O
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Differential PECL high-speed serial I/O
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Single +5 volt power supply
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Lock Detect & Frame Detect output
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Typical power dissipation of only 2.8 watts
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Seamless operation with PMC-Sierra's PM5355
S/UNI-622
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Backward compatible with SY69712
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New improved OOF circuitry
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Available in compact 100-pin thermally enhanced
QFP package
Synergy's SY69712A Transceiver with integrated clock
recovery contains a fully-integrated SONET OC-12 (622.08
Mbit/s) interface circuit. This device performs all necessary
serial-to-parallel and parallel-to-serial conversions per
SONET and SDH standards. The SY69712A is
manufactured in Synergy's high-performance, highly reliable
ASSET technology. It is ideally suited for SONET-based
ATM applications.
On-chip clock generation is performed by a low-jitter
phase-locked loop (PLL), allowing use of the 19.44MHz,
51.84MHz or 77.76MHz clock as a reference. Clock recovery
is performed by synchronizing the on-chip VCO directly to
the incoming data stream. The SY69712A can also perform
SONET/SDH frame detection and alignment on the input
data stream.
Compliance with the bit-error rate requirements of the
Bellcore, ITU/CCITT and ANSI standards is ensured by
Synergy's advanced PLL technology and Positive-ECL
(PECL) I/O.
BLOCK DIAGRAM
SONET/SDH/ATM OC-12 CLOCK
RECOVERING TRANSCEIVER
1999 Micrel-Synergy
Rev.: B
Amendment: /0
Issue Date: May, 1998
NETWORK
INTERFACE
8
8
T
X
R
X
R
X
T
X
8
8
NETWORK
INTERFACE
SY69712A
SY69712A
O/E
E/O
O/E
E/O
PRELIMINARY
INFORMATION
SY69712A
5-631
PINOUT
INPUTS
SDINP, SDINN [Serial Data Input] Differential PECL.
These pins are normally connected to the optical receiver
module. Clock is recovered from the transitions on the SDINP
and SDINN inputs.
PDI[7:0] [Parallel Data Input] TTL.
A 77.76 Mbyte/s word aligned to the XMBTCK transmit
byte clock. PDI7 is the most significant bit (corresponding
to bit 1 of each PCM word, the first bit transmitted). PDI[7:0]
is sampled on the rising edge of XMBTCK.
OOF [Out Of Frame Input] TTL.
The OOF interface has been changed to be directly
compatible with systems implementing OOF as a level-
sensitive signal, such as the PMC-Sierra PM5355, without
requiring any external circuitry. This change only affects
PIN DESCRIPTIONS
how the OOF input will initiate Frame Recovery and does
not change the way the Frame Detection is implemented.
The timing of the FRMDET and Parallel Data Outputs (PDO
[7:0]) remains unchanged.
OOF will initiate Frame Recovery (Byte Alignment) after
a rising edge on OOF is detected. The duration of OOF can
be a positive going pulse with a minimum width of one
RCVBTCK period or it can be a high level. In either case,
Frame Recovery will be enabled until the first valid 48-bit
framing sequence is detected (A1-A1-A1-A2-A2-A2) and a
Frame pulse is generated.
Once this sequence is detected, Frame Recovery is
disabled, but Frame Detection remains enabled. Therefore
any subsequent 48-bit framing sequence, as long as it is
byte-aligned with the initial framing sequence, will be
detected and cause a FRMDET pulse to be generated.
SYNERGY
SEMICONDUCTOR
1
31
51
81
TOP VIEW
GND
GND
GND
LOS
TGND
PDI7
TV
CC
TGND
PDI6
PDI5
PDI4
V
CC
V
CC
PDI3
PDI2
PDI1
TGND
TV
CC
PDI0
RF19SEL
RFCKIN
GND
GND
N/C
AGND
CK622SEL
RECKSEL
V
CC
GND
CK622P
CK622N
TGND
SDINP
SDINN
V
CC
V
CC
TV
CC
RFCKOUT
RCVBTCK
TGND
AGND
PLL1N
PLL1P
PLL1DIS
AV
CC
V
CC
V
CC
V
CC
XMBTCK
FRMDET
LCKDET
TV
CC
TGND
OOF
PDO7
PDO6
GND
GND
PDO5
PDO4
PDO3
TGND
TV
CC
PDO2
PDO1
PDO0
V
CC
V
CC
AV
CC
AGND
AV
CC
TGND
RSTN
FCLPBK
TMLPBK
V
CC
V
CC
SDOUTN
SDOUTP
RF77SEL
V
CC
XECKSEL
EXTCKN
EXTCKP
OOFLSEL
V
CC
PLL2DIS
PLL2P
PLL2N
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
PRELIMINARY
INFORMATION
SY69712A
5-632
If the first 48-bit sequence is a mimic frame and OOF is
never lowered (remains as a high level), then the SY69712A
will re-enable Frame Recovery after two frame times have
elapsed (>250
s). This will continue as long as OOF is held
high.
The SY69712A does not require any external circuitry
with the OOF input and will be compatible with any
implementation using the current SY69712.
OOFLSEL [Out of Frame Level] TTL.
This input is no longer necessary and should be treated
as a "don't care" since the OOF input has been revised.
This pin should not remain floating, and should be tied to
either VCC or GND.
RFCKIN [Reference Clock Input] TTL/PECL.
Input normally used to generate the XMBTCK. This signal
is also used to generate the "training" frequency for the
clock recovery circuit to keep it centered at 622.08MHz in
the absense of data coming in on the SDINP, SDINN inputs.
The RFCKIN can be either 19.44MHz, 51.84MHz (TTL) or
77.76MHz (PECL, single-ended) and can be selected with
RF19SEL and RF77SEL.
RF77SEL [Reference Clock High Frequency Select
Input] TTL.
A low lets the SY69712A default to the RF19SEL pin to
determine if this input frequency is 19.44MHz or 51.84MHz.
If this pin is high, then the SY69712A will be set for a
77.76MHz (PECL, single-ended) input frequency.
RF19SEL [Reference Clock Select Input] TTL.
Signal used to select the RFCKIN frequency. A high
selects 19.44MHz as the Reference Clock and a low selects
51.84MHz as the Reference Clock. A 51.84MHz or
77.76MHz reference clock should be used in SONET
applications.
LOS [Loss of Signal] PECL.
A single-ended active high input to be driven by the
external optical receiver module to indicate a loss of received
optical power. When LOS is high, the data on the Serial
Data Input (SDINP, SDINN) pin will be internally forced to a
constant low (zero), LCKDET forced low, and the clock
recovery PLL forced to lock to the 622.08MHZ clock
generated from the RFCKIN. When LOS is low, data on the
SDINP, SDINN pins will be processed normally.
TMLPBK [Terminal Loopback] TTL. (Active Low)
Selects terminal loopback diagnostic mode. When
TMLPBK is low, the parallel data presented on PDI[7:0] is
looped back via the serial receive side and presented back
on the PDO[7:0] along with the recovered clock. Should be
high for normal operation.
PIN DESCRIPTIONS
FCLPBK [Facility Loopback] TTL. (Active Low)
Selects facility loopback diagnostic mode. When FCLPBK
is low, the serial data coming on the SDINP, SDINN pins is
routed out via the SDOUTP, SDOUTN pins. Should be high
for normal operation.
RSTN [Master Reset] TTL. (Active Low)
An active low signal that resets the device. Frame
detection is disabled after master reset. RSTN must be low
for 1 millisecond minimum. Should be HIGH for normal
operation.
PLL1N, PLL1P [Loop Filter 1]
Loop filter pins for the clock recovery PLL.
PLL2N, PLL2P [Loop Filter 2]
Loop filter pins for the clock synthesis PLL.
PLL1DIS, PLL2DIS [PLL Disable] TTL.
Normally connected to AGND these inputs can be used
to disable the respective PLLs for test purposes. These are
active high inputs. (i.e., a high on PLL1DIS will disable the
clock recovery PLL.)
CK622SEL [622.08MHz Clock Out Select] TTL.
A high on this pin will present the external 622.08MHz
clock on the CKE622P and CKE622N pins. A low disables
the output and minimizes noise.
XECKSEL [Transmit External Clock Select] TTL.
A high on this pin allows the EXTCKP and EXTCKN
inputs to be used as the 622.08MHz transmit clock. This is
tied to TGND for normal (internal clock recovery) operation.
RECKSEL [Receive External Clock Select] TTL.
A high on this pin allows the EXTCKP and EXTCKN
inputs to be used as recovered clock inputs. This makes it
possible to use this device with optical receiver modules
that provide on-board clock recovery. This is tied to TGND
for normal (internal clock recovery) operation.
EXTCKP, EXTCKN [External 622.08MHz Clock Input]
Differential PECL.
These pins are normally connected to the optical receiver
module that has on-board clock recovery.
OUTPUTS
SDOUTP, SDOUTN [Serial Data Output] Differential
PECL.
These pins are normally connected to the optical
transmitter module.
SYNERGY
SEMICONDUCTOR
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