SY58626L

DC-to-6.4Gbps Backplane Transmit Buffer

with Selectable Output Pre-emphasis, I/O DC-

Offset Control, and 200mV-3.0V

Output

Swing

Precison Edge is a registered trademark of Micrel, Inc.
MLF and

Micro

LeadFrame are trademarks of Amkor Technology, Inc.

Micrel Inc. · 2180 Fortune Drive · San Jose, CA 95131 · USA · tel +1 (408) 944-0800 · fax + 1 (408) 474-1000 · http://www.micrel.com

September 2005

M9999-093005-A

hbwhelp@micrel.com

or (408) 955-1690

General Description

The SY58626L high-speed, low jitter transmit buffer is
optimized for backplane and transmission line data-path
management applications in Automatic Test Equipment
(ATE) and Test & Measurement (T&M) systems. The
buffer includes a CML compatible, variable swing output
with selectable pre-emphasis. The SY58626L is
capable of driving serial data from DC through 6.4Gbps
with a 3V

(1.5V

single ended) differential swing.

The SY58626L differential input includes Micrel's
unique, 3-pin input termination architecture that directly
interfaces to any DC- or AC-coupled, differential signal
as small as 100mV

without any termination resistor

networks in the signal path. The outputs are 50

source-terminated CML with a programmable output
swing from 200mV

to 3V

(100mV

to 1.5V

The SY58626L includes an output stage that provides 4
levels of pre-emphasis. The output pre-emphasis level is
programmed with a three-bit interface. Unlike other
transmitter solutions, the output pre-emphasis duration
can be programmed from 60ps to 400ps.
The SY58626L operates at 3.3V ±10% supply and is
guaranteed over the commercial temperature range of
0°C to +70°C. The SY58626L transmitter is optimized to
work with the SY58627L receiver. The SY58626L is part
of Micrel's high-speed, Precision Edge

product line.

Data sheets and support documentation can be found
on Micrel's website at: www.micrel.com.

Precision Edge®

Features

· Transmit driver provides output pre-emphasis to

extend transmission range

· 4 selectable pre-emphasis levels
· Drives 6.4Gbps up to 12

" FR4 PCB trace, or longer

combinations of FR4+cable+interconnect

· DC through 6.4Gbps data rate throughput
· Integrated loopback

capability

· Unique pre-emphasis:
- Programmable pre-emphasis magnitude
- Programmable pre-emphasis duration
· Unique, flexible I/O:

- Internal termination to VTTIN pin interfaces to any

differential AC- or DC-coupled signals

50 source terminated CML outputs minimize
round-trip reflections

- Programmable output swing control: 200mV-

3.0V

- Output Disable and output shutdown
- DC-offset control with VTT I/O
· 3.3V ±10% supply voltage
· 0°C to +70°C temperature range
· Available in 32-pin (5mm x 5mm) MLF

package

Applications

· ATE, T&M backplane management
· Combination FR4+cable+interconnect driver
· Cable drivers
· Electrical interface and interconnect applications that

require DC-offset control

Micrel, Inc.

SY58626L

September 2005

M9999-093005-A

hbwhelp@micrel.com

or (408) 955-1690

Pin Description

Pin Number

Pin Name

Pin Function

4, 5

TXIN, /TXIN

Differential inputs: This input pair is the differential signal input to the device. They
accept AC- or DC-coupled signals as small as 100mV (200mV

). Note that this

input will default to an undetermined state if left open. TXIN and /TXIN internally
terminate to the VTTIN

pin through 50. Please refer to the "Input Interface

Applications" section for more details.

7 VTTIN

Input termination center-tap: TXIN and /TXIN terminate to VTTIN. The VTTIN pin
provides a center-tap to the internal termination network for maximum interface
flexibility and DC-offset capability. Please refer to the "Input Interface Applications"
section for more details.

8 VREF-AC

Reference voltage: This output biases to V

-1.3V. It is used for AC-coupling the

input pair (TXIN, /TXIN). Connect VREF-AC directly to the VTTIN pin. Bypass with a
0.01uF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Due to
the limited drive capability, the VREF-AC pin is only intended to drive the VTTIN pin.
Please refer to the "Input Interface Applications" section for more details.

13 TXVCTRL

Analog input that controls TXQ output swing amplitude. The operating range of the
control input is from VREF-CTRL (max swing) to VCC (min swing). Control of the
output swing can be obtained by using a variable resistor between VREF-CTRL and
VCC with the wiper driving TXVCTRL. Output swing ranges from 100mV

1.5V

. When the TXQ output is selected for maximum swing amplitude of 1.5V

no pre-emphasis is possible since the maximum swing cannot extend beyond
1.5V

. For applications that only require a fixed, full CML swing, connect

TXVCTRL to VREF-FIXED.

12 VREF-CTRL

Reference control voltage for TXVCTRL swing control. The operating range of the
control input is from VREF-CTRL (max swing) to VCC (min swing). Control of the
output swing can be obtained by using a variable resistor between VREF-CTRL and
VCC with the wiper driving TXVCTRL. Maximum sink/source current is ±1.5mA.

14 VREF-FIXED

Reference output voltage: Connect this reference output pin directly to the
TXVCTRL input pin, and the TXQ output swing is fixed to 400mV

(800mV

24 /TXEN

TTL/CMOS (or VTH controlled) compatible control input for the TXQ Outputs pair.
When pulled HIGH, the TXQ Output pair is disabled. This input is internally
connected to a 25k

pull-down resistor and will default to a logic LOW state

(Enable) if left open. When disabled, the TXQ output goes LOW, and /TXQ goes
HIGH. Default threshold is Vcc/2 when VTH pin is floating.

29 /TXLBEN

TTL/CMOS (or VTH controlled) compatible control input for the TXLBQ output pair.
When pulled HIGH, the TXLBQ output pair is disabled. This input is internally
connected to a 25k

pull-down resistor and will default to a logic LOW state

(Enable) if left open. When disabled, the TXLBQ output goes LOW, and /TXLBQ
goes HIGH. Default threshold is Vcc/2 when VTH pin is floating.

1 LBSEL

Loopback MUX select control: The TTL/CMOS (or VTH controlled) compatible input
selects the input to the Loopback mode multiplexer. When LBSEL input is a logic
HIGH, the Loopback mode is selected, and the RXLBIN input pair is selected to
pass through the TXQ output. Note that the LBSEL pin is internally connected to a
25k

pull-down resistor and will default to a logic LOW state if left open (normal

operation). The loopback MUX includes internal input isolation to minimize
crosstalk.

30, 31

RXLBIN,
/RXLBIN

Loopback differential input pair: AC-coupled, CML compatible input. This input pair
includes internal termination connected to an internal VBB for an AC-coupled bias
configuration. The RXLBIN input pair receives a signal from the RX buffer
(SY58627L RXLBQ) loopback output. This input pair does not include any
equalization. When Loopback mode is selected, the signal at the RXLBIN input is
directed to the TXQ output.

Micrel, Inc.

SY58626L

September 2005

M9999-093005-A

hbwhelp@micrel.com

or (408) 955-1690

Pin Description

(Continued)

Pin Number

Pin Name

Pin Function

27, 28

TXLBQ,
/TXLBQ

Transmit loopback differential output: CML compatible output pair with 400mV swing
into a 50

load (100 across the pair). The TXLBQ output pair is providing a copy of

the TXIN input signal, bypassing the pre-emphasis stage. The SY58626L loopback
function is optimized to operate with the SY58627L receiver, and the TXLBQ output
pair is AC-coupled directly to the TXLBIN input pair on the SY58627L.

23 /TXQSHDN

TXQ shutdown control pin: The TTL/CMOS (or VTH controlled) compatible pin is an
active LOW function. This input is internally connected to a 25k pull-up resistor and
will default to a logic HIGH state if left open. When pulled LOW, the TXQ and /TXQ
output currents are shut off, and the TXQ and /TXQ output voltage is set to the same
potential. The actual voltage level is set by the resistor divider ratio established by
the internal 50

source resistors (connected to VTTOUT) and the external load.

Default threshold is Vcc/2 when VTH pin is floating.

2 VTH

Input logic threshold control voltage for logic control threshold settings other than
LVTTL/CMOS. This input control pin can be externally biased to set the proper
threshold for all the logic control pins, /TXEN, LBSEL, /TXLBEN, 3-bit pre-emphasis
control, 2-bit pre-emphasis duration control, and /TXQSHDN. For standard
LVTTL/CMOS control, simply leave the VTH pin floating and the threshold voltage
defaults to V

/2 (When VEE=0V). For LVPECL thresholds, set VTH to Vcc-1.3V.

21, 20

TXQ,
/TXQ

Differential variable swing output pair: This CML output pair is the output of the
device. This output is designed to drive 100mV

to 1.5V

into 50

(100 across

the pair) with variable pre-emphasis. TXQ outputs include 50

source termination

resistors. When the loopback mode is selected, the TXQ output pair is driven by the
RXLBIN inputs.

19, 22

VTTOUT

Output termination center-tap: Each side of the differential output pair terminates to
the VTTOUT

pin through 50

. The VTTOUT pin provides a center-tap to the output

termination network for maximum interface flexibility, and DC-offset capability.
Please refer to the "CML Output Interface Applications" section for more details.

17
18
32

MAG_CTRL0
MAG_CTRL1
MAG_CTRL2

Pre-emphasis magnitude level control input: TTL/CMOS (or VTH controlled)
compatible, 3-bit control interface. There are four levels of pre-emphasis magnitude,
as shown in the "Pre-Emphasis Magnitude Truth Table." When MAG_CTRL2 (MSB)
is logic 1, pre-emphasis is disabled and the TXQ outputs will not include any pre-
emphasis. Pre-emphasis magnitude ranges from 10% to 33% above the base swing.

10
11

DUR_CTRL0
DUR_CTRL1

Pre-emphasis duration control input. TTL/CMOS (or VTH controlled) compatible, 2-bit
control interface. This control establishes the pre-emphasis duration. Duration ranges
from 60ps to 400ps typical as shown in the "Pre-emphasis Duration Control Truth
Table." Pre-emphasis duration is measured from the mid-point of the pre-emphasis
magnitude (50% point). Please refer to the "Pre-emphasis Output Description" for
details.

9, 15, 26

VCC

Positive power supply: Connect to +3.3V power supply. Bypass with 0.1µF//0.01µF
low ESR capacitors as close to VCC pins as possible.

3, 6, 16, 25

VEE,

Exposed Pad

Ground: Ground pins and exposed pad must be connected to the same ground
plane.

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