1
Precision EdgeTM
SY58025U
Micrel
M9999-051804
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s
Two independent differential 2:1 multiplexers
s
Guaranteed AC performance over temperature and
voltage:
DC-to >10.7Gbps data rate throughput
<290ps IN-to-Out t
pd
<70ps t
r
/ t
f
times
s
Unique, patent-pending input isolation design
minimizes crosstalk
s
Ultra-low jitter design:
<1ps
rms
random jitter
<10ps
pp
deterministic jitter
<10ps
pp
total jitter (clock)
<0.7ps
rms
crosstalk-induced jitter
s
Unique, patent-pending 50
input termination and
VT pin accepts DC-coupled and AC-coupled inputs
(CML, LVDS, PECL)
s
Typical 400mV CML output swing (R
L
= 50
)
s
Internal 50
input termination
s
Power supply 2.5V
5% or 3.3V
10%
s
40
C to +85
C temperature range
s
Available in 32-pin (5mm
5mm) MLFTM package
FEATURES
ULTRA PRECISION DUAL 2:1 CML
MUX WITH INTERNAL I/O TERMINATION
Precision EdgeTM
SY58025U
APPLICATIONS
s
Data communication systems
s
All SONET OC3-OC-768 applications
s
All Fibre Channel applications
s
All GigE applications
Rev.: A
Amendment: /0
Issue Date:
May 2004
The SY58025U features two ultra-fast, low jitter 2:1
differential muxes with a guaranteed maximum data or clock
throughput of 10.7Gbps or 7GHz, respectively.
The SY58025U differential inputs include a unique,
internal termination design that allows access to the
termination network through a VT pin. The device easily
interfaces to different logic standards, both AC- and DC-
coupled, without external resistor-bias and termination
networks. The result is a clean, stub-free, low jitter interface
solution. The differential CML output is optimized for 50
environments with internal 50
source termination and a
400mV output swing.
The SY58025U operates from a 2.5V or 3.3V supply and
is guaranteed over the full industrial temperature range
(40
C to +85
C). The SY58025U is part of Micrel's Precision
EdgeTM product family.
All support documentation can be found on Micrel's web
site at www.micrel.com.
FUNCTIONAL BLOCK DIAGRAM
AnyGate and Precision Edge are trademarks of Micrel, Inc.
Micro
LeadFrame and MLF are trademarks of Amkor Technology, Inc.
Precision EdgeTM
QA
/QA
INA0
/INA0
V
TA0
50
50
INA1
V
REF-ACA0
/INA1
V
TA1
50
50
V
REF-ACA1
0
1
MUX A
SELA
(TTL/CMOS)
S
QB
/QB
INB0
/INB0
V
TB0
50
50
INB1
V
REF-ACB0
/INB1
V
TB1
50
50
V
REF-ACB1
0
1
MUX B
SELB
(TTL/CMOS)
S
2
Precision EdgeTM
SY58025U
Micrel
M9999-051804
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information
(1)
Package
Operating
Package
Part Number
Type
Range
Marking
SY58025UMI
MLF-32
Industrial
SY58025U
SY58025UMITR
(2)
MLF-32
Industrial
SY58025U
Notes:
1. Contact factory for die availability. Dies are guaranteed at T
A
= 25
C,
DC electricals only.
2. Tape and Reel.
Pin Number
Pin Name
Pin Function
25, 28,
INA0, /INA0,
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
29, 32,
INA1, /INA1,
accept AC- or DC-coupled differential signals as small as 100mV. Each pin of a pair
1, 4,
INB0, /INB0,
internally terminates to a V
T
pin through 50
. Note that these inputs will default to an
5, 8
INB1, /INB1
indeterminate state if left open. Unused differential input pairs can be terminated by
connecting one input to V
CC
and the complementary input to GND through a 1k
resistor.
The VT pin is to be left open in this configuration. Please refer to the "Input Interface
Applications" section for more details.
26, 30, 2, 6
VTA0 , VTA1,
Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT
VTB0, VTB1
pin. Each V
T
pin provides a center-tap to a termination network for maximum interface
flexibility. See "Input Interface Applications" section for more details.
18, 15
SELA, SELB
Bank A, Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible inputs
select the inputs to the multiplexers. These inputs are internally connected to a 25k
pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold
is V
CC
/2.
27, 31, 3, 7
VREF-ACA0,
Reference Output Voltage: These outputs bias to V
CC
1.2V. Connect to the VT pin when
VREF-ACA1,
AC-coupling the data inputs. Bypass with 0.01
F low ESR capacitor to V
CC
. Maximum
VREF-ACB0,
current source or sink is 0.5mA. See "Input Interface Applications" section.
VREF-ACB1
10, 13, 16,
VCC
Positive Power Supply: Bypass with 0.1
F
0.01
F low ESR capacitors.
17, 20, 23
22, 21,
QA, /QA,
Differential CML Outputs: MUX A and MUX B selected CML outputs. See "Output
12, 11
QB, /QB
Interface Applications" section for termination. Refer to the "Truth Table" for logic
operation.
9, 24
GND,
Ground: Ground pin and exposed pad must be connected to the same ground plane.
Exposed pad
14, 19
NC
Not connected.
PIN DESCRIPTION
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
32 3130 29 28 27 26 25
INB0
VTB0
VREF-ACB0
/INB0
INB1
VTB1
VREF-ACB1
/INB1
GND
VCC
QA
/QA
VCC
NC
SELA
VCC
/INA0
INA1
VT
A1
VREF-ACA1
/INA1
VREF-ACA0
VT
A0
INA0
VCC
QB
/QB
VCC
GND
NC
SELB
VCC
32-Pin MLFTM (MLF-32)
3
Precision EdgeTM
SY58025U
Micrel
M9999-051804
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings
(1)
Power Supply Voltage (V
CC
) ...................... 0.5V to +4.0V
Input Voltage (V
IN
) ......................................... 0.5V to V
CC
CML Output Voltage (V
OUT
) ........... V
CC
1.0V to V
CC
+0.5V
Termination Current
(3)
Source or sink current on V
T
pin ........................
100mA
Input Current
Source or sink current on IN, /IN pin ....................
50mA
Current (V
REF-AC
)
Source or sink current on V
REF-AC
(3)
..................
1.5mA
Lead Temperature (soldering, 10 sec.) ..................... 265
C
Storage Temperature Range (T
S
) ........... 65
C to +150
C
Operating Ratings
(2)
Power Supply Voltage (V
CC
) ............... +2.375V to +2.625V
............................................................ +3.0V to +3.6V
Ambient Temperature Range (T
A
) ............. 40
C to +85
C
Package Thermal Resistance
(4)
MLFTM (
JA
)
Still-Air ............................................................. 35
C/W
MLFTM (
JB
)
Junction-to-board ............................................ 20
C/W
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC
Power Supply
V
CC
= 2.5V
2.375
2.5
2.625
V
V
CC
= 3.3V
3.0
3.3
3.6
V
I
CC
Power Supply Current
No load, max. V
CC
.
(6)
115
140
mA
R
DIFF_IN
Differential Input Resistance
80
100
120
(IN-to-/IN)
R
IN
Input Resistance
40
50
60
(IN-to-V
T
, /IN-to-V
T
)
V
IH
Input High Voltage (IN, /IN)
V
IN
must be
1.2V.
V
CC
1.6
V
CC
V
V
IL
Input Low Voltage (IN, /IN)
0
V
IH
0.1
V
V
IN
Input Voltage Swing (IN, /IN)
See Figure 1a.
0.1
1.7
V
V
DIFF_IN
Differential Input Voltage Swing
See Figure 1b.
0.2
3.4
V
|IN - /IN|
V
T IN
In to V
T
(IN, /IN)
1.28
V
V
REF-AC
Output Reference Voltage
V
CC
1.3 V
CC
1.2 V
CC
1.1
V
Notes:
1. Permanent device damage may occur if the ratings in "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional
operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability, use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential (GND) on the PCB.
JB
uses 4-
layer
JA
in still air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Includes current through internal 50
pull-ups. See Figure 1b.
DC ELECTRICAL CHARACTERISTICS
(5)
T
A
= 40
C to +85
C; unless otherwise stated.
4
Precision EdgeTM
SY58025U
Micrel
M9999-051804
hbwhelp@micrel.com or (408) 955-1690
V
CC
= 2.5V
5% or 3.3V
10%; T
A
= 40
C to +85
C; R
L
= 100
across each output pair, or equivalent, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
Output High Voltage
V
CC
0.020
V
CC
V
Q, /Q
V
OUT
Output Voltage Swing
See Figure 1a.
325
400
mV
Q, /Q
V
DIFF-OUT
Differential Output Voltage Swing
See Figure 1b.
650
800
mV
Q, /Q
R
OUT
Output Source Impedance
40
50
60
Q, /Q
CML OUTPUT DC ELECTRICAL CHARACTERISTICS
(7)
V
CC
= 2.5V
5% or 3.3V
10%; T
A
= 40
C to 85
C unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
V
V
IL
Input LOW Voltage
0.8
V
I
IH
Input HIGH Current
125
50
A
I
IL
Input LOW Current
300
A
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(7)
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5
Precision EdgeTM
SY58025U
Micrel
M9999-051804
hbwhelp@micrel.com or (408) 955-1690
V
CC
= 2.5V
5% or 3.3V
10%; T
A
= 40
C to +85
C; R
L
= 100
across each output pair, or equivalent, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
NRZ Data
10.7
Gbps
V
OUT
200mV
Clock
6
GHz
t
pd
Propagation Delay
IN-to-Q
140
290
ps
SEL-to-Q
100
400
ps
t
SKEW
Input-to-Input Skew (Within-Bank)
Note 9
3
15
ps
Bank-to-Bank Skew
Note 10
5
20
ps
Part-to-Part Skew
Note 11
100
ps
t
JITTER
Data
Random Jitter (RJ)
Note 12
1
ps
rms
Deterministic Jitter (DJ)
Note 13
10
ps
pp
Clock
Cycle-to-Cycle Jitter
Note 14
1
ps
rms
Total Jitter (TJ)
Note 15
10
ps
pp
Crosstalk-Induced Jitter
Channel-to-Channel
Note 16, Within-bank.
0.7
ps
rms
t
r
, t
f
Output Rise/Fall Time 20% to 80%
At full swing.
20
50
70
ps
Notes:
8. High-speed AC parameters are guaranteed by design and characterization. V
IN
swing
100mV unless otherwise noted.
9. Input-to-input skew is the difference in time between two inputs to the output within a bank.
10. Bank-to-bank skew is the difference in time from input to the output between bank.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
12. Random jitter is measured with a K28.7 comma detect character pattern, measured at 10.7Gbps and 2.5Gbps/3.2Gbps.
13. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 2
23
1 PRBS pattern
14. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n
T
n1
where T is the time between rising edges of the output
signal.
15. Total jitter definition: with an ideal clock input of frequency
f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
16. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
AC ELECTRICAL CHARACTERISTICS
(8)
TRUTH TABLES
INA0
/INA0
INA1
/INA1
SELA
QA
/QA
0
1
X
X
0
0
1
1
0
X
X
0
1
0
X
X
0
1
1
0
1
X
X
1
0
1
1
0
INB0
/INB0
INB1
/INB1
SELB
QB
/QB
0
1
X
X
0
0
1
1
0
X
X
0
1
0
X
X
0
1
1
0
1
X
X
1
0
1
1
0
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