1
SuperLiteTM
SY55856U
Micrel
DESCRIPTION
s
Guaranteed AC parameters over temp and voltage
> 2.5GHz F
MAX
< 384ps prop delay
< 120ps T
r
/T
f
s
Delay either clock or data
s
50ps increments
s
350ps total delay
s
Delay either clock or data
s
Source terminated CML outputs
s
Full differential I/O
s
Wide supply voltage spectrum: 2.3V to 3.6V
s
Available in a tiny 32-pin EPAD-TQFP package
FEATURES
2.5V/3.3V 2.5GHz
DIFFERENTIAL 2-CHANNEL
PRECISION CML DELAY LINE
SuperLiteTM
SY55856U
FINAL
APPLICATIONS
s
Data communications systems
s
Telecom systems
s
High-speed backplanes
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Signal de-skewing
s
Pulse alignment
s
Digitally controlled delay lines
PIN CONFIGURATION
Rev.: B
Amendment: /0
Issue Date:
March 2003
Pin
Function
CLK_IN,
Differential Clock Input (CML compatible)
/CLK_IN
CLK_OUT,
Differential Clock Output (CML)
/CLK_OUT
CINV
Clock Inversion Control (CML compatible)
DATA_IN,
Differential Data Input (CML compatible)
/DATA_IN
DATA_OUT,
Differential Data Output (CML)
/DATA_OUT
LVL
Control Level Select (CML compatible)
DELAY_SEL
Delay Path Control (CML compatible)
S2, S1, S0
Delay Selection Control (LSB=S0)
GND
Ground
V
CC
V
CC
PIN NAMES
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Top View
EPAD-TQFP
H32-1
/DATA_IN
GND
DATA_IN
GND
GND
CLK_IN
GND
/CLK_IN
/DATA_OUT
GND
DATA_OUT
GND
GND
CLK_OUT
GND
/CLK_OUT
VCC
VCC
CINV
NC
NC
LV
L
VCC
VCC
VCC
VCC
DELA
Y_SEL
S2
S1
S0
VCC
VCC
The SY55856U is a 2.5GHz, two-channel, fully differential
CML (Current Mode Logic) delay line. The device is
optimized to adjust the relative delay between two channels,
such as clock and data, in 50ps increments. Both inputs
may be adjusted in either direction in 7 increments of 50ps,
for a total adjustment range of
350ps. In addition, the
clock input maybe inverted through the CINV control pin.
The SY55856U inputs are designed to accept single-
ended or differential CML signals. The differential CML
outputs are optimized for 50
loads (50
source terminated),
thus only requires a single 100
resistor across the output
pair. Output rise and fall time is an extremely fast 110ps(max)
and the differential swing is 400mV. The maximum
throughput of the SY55856U is guaranteed to exceed
2.5GHz (1.25Gbps).
SuperLite is a trademarks of Micrel, Inc.
SuperLiteTM
2
SuperLiteTM
SY55856U
Micrel
BLOCK DIAGRAM
A7
S0
S1
S2
A6
A5
A4
A3
A2
A1
A0
A7
S0
5k
5k
S1
S2
A6
DATA_OUT
/DATA_OUT
S2
S1
S0
DEL_SEL
CLK_OUT
/CLK_OUT
GND
CINV
/CLK_IN
CLK_IN
LVL
/DATA_IN
DATA_IN
VCC
A5
A4
A3
A2
A1
A0
INPUT
BUFFER
V
REF
= 1.3V
INPUT
BUFFER
PIN DESCRIPTIONS
CLK_IN, /CLK_IN CML Input (Differential)
This is one of the differential CML inputs, the clock in signal.
A delayed version of this input appears at CLK_OUT,
/CLK_OUT.
CINV VT Input (Single Ended)
This is the clock inversion select signal. This input optionally
inverts the CLK_IN, /CLK_IN signal which results in an
inverted CLK_OUT, /CLK_OUT. A voltage below the VT
threshold results in no inversion. A voltage above the
threshold value results in an inversion from the clock input
to the clock output. Refer to the "VT input" section below.
CLK_OUT, /CLK_OUT CML Output (Differential)
This is one of the CML outputs, the clock output. It is a
delayed, copy of CLK_IN, /CLK_IN.
DATA_IN, /DATA_IN CML Input (Differential)
This is one of the CML inputs, the data in signal.
A delayed version of this signal appears at DATA_OUT,
/DATA_OUT.
DATA_OUT, /DATA_OUT CML Output (Differential)
This is one of the CML outputs, the data output. It is a
delayed version of CLK_IN, /CLK_IN.
LVL Analog Input
This input determines what level differentiates logic high
from logic low. This input affects the behavior of the CINV,
S0, S1 and S2 inputs. Please refer to the "VT input" section
below for more details. For the control interface, see Figure
3b. For TTL control interface, see Figure 3b.
DELAY_SEL VT Input (Single Ended)
CML compatible control logic. This is the delay path control
input. Logic high delays the clock signal with respect to the
data signal. A logic low delays the data signal with respect
to the clock signal. Inputs S2, S1 and S0 control amount of
delay.
S0, S1, S2 VT Input (Single Ended)
CML compatible control logic. This is the delay selection
control input. These three bits define how much relative
delay will occur between the data and clock signals, as per
the truth table shown in Table 2. For the control logic
interface, see Figure 3b. For TTL control interface, see
Figure 3b. S0=LSB.
3
SuperLiteTM
SY55856U
Micrel
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs
The true pin of a CML input pair is internally biased to
ground through a 75k
resistor. The complement pin of a
CML input pair is internally biased halfway between V
CC
and ground by a voltage divider consisting of two 75k
resistors. To keep a CML input at static logic zero at V
CC
>
3.0V, leave both inputs unconnected. For V
CC
3.0V,
connect the complement input to V
CC
and leave the true
input unconnected. To make an input static logic one,
connect the true input to V
CC
, and leave the complement
input unconnected. These are the only safe ways to cause
CML inputs to be at a static value. In particular, no CML
input should be directly connected to ground. All NC pins in
the figures below should be left unconnected.
VT (Variable Threshold) Inputs
Five inputs to SY55856U, CINV, DELAY_SEL, S0, S1, and
S2, are variable threshold inputs. The LVL input determines
the Voltage threshold that differentiates logic high from logic
low for these five inputs only. If LVL is left unconnected, the
VT inputs will switch at about
V
GND
2
CC
+
or V
TCL
,
whichever is higher. To obtain a logic switching threshold
different from this, the LVL input must be driven with the
actual desired threshold voltage. The user may drive the
LVL pin with any voltage between V
CC
0.1V and ground.
For example, driving LVL with a voltage set at Vcc 1.3V
causes the VT inputs to accept single ended PECL outputs
and switch appropriately.
Note that VT inputs are internally clamped so that the
threshold will not fall below VTCL Volts. Since driving the
LVL input to ground causes the threshold to be somewhere
between V
TCL
(min) and V
TCL
(max), it is expected that the
user will keep the Voltage at the LVL pin at or above V
TCL
(max). Please refer to Figure 3 for clarification.
V
CC
NC
IN
/IN
Figure 1. Hard Wiring a Logic "1"
(1)
NC
V
CC
> 3.0V
NC
IN
/IN
NC
V
CC
3.0V
VCC
IN
/IN
Figure 2. Hard Wiring a Logic "0"
(1)
Operating
Range
V
TCL
V
TCL
V
CC
-- 0.1V
V
CC
-- 0.1V
V
CC
V
CC
LVL
Input
Logic
Switching
Threshold
Figure 3a. Logic Switching Threshold
3
V
CC
3.0V
V
CC
3.6V
SY55856
909
1.10k
S0, S1, S2
LVL
TTL
Driver
V
CC
Figure 3b. Interfacing TTL-to-CML Select
(CINV, DELAY_SEL, S0, S1, S2)
Note 1.
IN is either the DATA_IN or the CLK_IN input. /IN is either the /
DATA_IN or the /CLK_IN input.
4
SuperLiteTM
SY55856U
Micrel
Symbol
Rating
Value
Unit
V
CC
Power Supply Voltage
0.5 to +6.0
V
V
IN
Input Voltage
0.5 to V
CC
+5.0
V
V
OUT
CML Output Voltage
0.5 to V
CC
+5.0
V
T
A
Operating Temperature Range
40 to +85
C
T
store
Storage Temperature Range
55 to +125
C
JA
Package Thermal Resistance
Still Air
28
C/W
(Junction-to-Ambient)
500lfpm
20
C/W
Exposed pad soldered to PCB GND pin
JC
Package Thermal Resistance
(Junction-to-Case)
4
C/W
Note 1.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation
is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM
RATlNG conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
CML TERMINATION
50
50
100
SY55856U
V
CC
16mA
50
50
Figure 4.
50
Load CML Output
All CML inputs accept a CML output from any other
member of this family. All CML outputs are source
terminated 50
differential drivers as shown in Figure 4.
SY55856U expects its inputs to be externally terminated.
SY55856U inputs are designed to accept a termination
resistor between the true and complement inputs of a CML
differential input pair, as shown in Figure 4.
5
SuperLiteTM
SY55856U
Micrel
TRUTH TABLES
Note 1.
Table 2 defines the approximate relative delay between the two paths. For example, if S2, S1, S0 = 000, and an edge appears at CLK_IN at
the same instant as an edge appears at DATA_IN, then an edge at CLK_OUT will appear about 350ps earlier than an edge at DATA_OUT.
That is, negative values imply CLK_OUT being shifted early with respect to DATA_OUT. Likewise, a positive value in the third column implies
that CLK_OUT is shifted late with respect to DATA_OUT. Please consult the "AC ELECTRICAL CHARACTERISTICS" section for more
precise delay values.
Note 2.
As another example, if an edge at CLK_IN appears 100ps before an edge at DATA_IN, and if S2, S1, S0 = 100, then an edge at CLK_OUT
will appear about 50ps after an edge at DATA_OUT. This setting of the select inputs shifts CLK_IN to CLK_OUT about 150ps later than
DATA_IN to DATA_OUT, moving the timing of the "C" side from 100ps early to 50ps late, as compared with the "D" channel, going through the
part.
S2
S1
S0
DATA_OUT
CLK_OUT
(CLK_OUTCLK_IN)
(D_SEL=0) (ps)
(D_SEL=1) (ps)
(DATA_OUTDATA_IN) (ps)
0
0
0
350
0
350
0
0
1
300
50
250
0
1
0
250
100
150
0
1
1
200
150
50
1
0
0
150
200
50
1
0
1
100
250
150
1
1
0
50
300
250
1
1
1
0
350
350
Table 2. Nominal Differential Delay Values
DATA_IN CLK_IN CINV
DATA_OUT
/DATA_OUT CLK_OUT /CLK_OUT
0
0
0
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
Table 1. Input to Output Connectivity
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