TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 1 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Features

Single chip solution with only a few external

components

Stand-alone fixed-frequency user mode

Programmable multi-channel user mode

Low current consumption in active mode and

very low standby current

PLL-stabilized RF VCO (LO) with internal

varactor diode

Lock detection in programmable user mode

On-chip AFC option for extended input

frequency acceptance range

3wire bus serial control interface

FSK/ASK modulation selection

FSK for digital data and FM for analog signal

reception

RSSI allows signal strength indication and ASK

reception

Switchable LNA gain for improved dynamic

range

Automatic PA turn-on after PLL lock

ASK modulation achieved by PA on/off keying

AFC option for extended input frequency

acceptance range

32-pin Low profile Quad Flat Package (LQFP)

Ordering Information

Part No.

Temperature Code

Package Code

TH7120

E (-40 °C to 85 °C)

NE (LQFP32)

Application Examples

General bi-directional half duplex digital data

transmission or analog signal transmission

Low-power

telemetry

Alarm and security systems

Remote Keyless Entry (RKE)

Tire Pressure Monitoring System (TPMS)

Garage door openers

Intelligent remote control

Home

automation

Pin Description

General Description

The TH7120 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multi-channel
programmable or single-channel stand-alone, half-duplex data transmission systems. It can be used for ISM,
SRD or any other application operating in the frequency ranging of 300 MHz to 930 MHz. In programmable
user mode, the transceiver can operate down to 27 MHz by employing an external VCO varactor diode.

_
I
F

SSI

T
A

_
I
F

/
S

VEE_

CC_

L
L

VEE_

I
G

_
L

OUT_PA

IN_LNA

OUT_LNA

VEE_IF

OUT_MIX

GAIN_LNA

IN_MIX

VEE_LNA

RE/SCLK

IN_DTA

ASK/FSK

FSK_SW
RO
VEE_RO

VCC_DIG

TH7120

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 2 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Document Content

Theory of Operation...................................................................................................4

1.1 General .............................................................................................................................. 4

1.2 Technical Data Overview ................................................................................................... 4

1.3 Block Diagram.................................................................................................................... 5

1.4 User Mode Features .......................................................................................................... 5

Pin Definitions and Descriptions ..............................................................................6

Functional Description ............................................................................................10

3.1 PLL Frequency Synthesizer ............................................................................................. 10

3.1.1

Reference Oscillator....................................................................................................................11

3.1.2

Reference Divider .......................................................................................................................11

3.1.3

Feedback Divider ........................................................................................................................11

3.1.4

Phase-frequency Detector ..........................................................................................................12

3.1.5

Lock Detector ..............................................................................................................................12

3.1.6

Voltage Controlled Oscillator with external Loop Filter ...............................................................13

3.1.7

Loop Filter ...................................................................................................................................13

3.2 Receiver Part ................................................................................................................... 13

3.2.1

LNA .............................................................................................................................................13

3.2.2

Mixer ...........................................................................................................................................13

3.2.3

IF Amplifier ..................................................................................................................................14

3.2.4

ASK Demodulator .......................................................................................................................14

3.2.5

FSK Demodulator........................................................................................................................14

3.3 Transmitter Part ............................................................................................................... 14

3.3.1

Power Amplifier ...........................................................................................................................14

3.3.2

Output Power Adjustment ...........................................................................................................14

3.3.3

Modulation Schemes...................................................................................................................15

3.3.4

ASK Modulation...........................................................................................................................15

3.3.5

FSK Modulation...........................................................................................................................15

3.3.6

Crystal Pulling .............................................................................................................................15

Description of User Modes......................................................................................16

4.1 Stand-alone User Mode Operation................................................................................... 16

4.1.1

Frequency Selection ...................................................................................................................16

4.2 Programmable User Mode Operation............................................................................... 17

4.2.1

Serial Control Interface Description ............................................................................................17

Register Description ................................................................................................18

5.1 Register Overview............................................................................................................ 18

5.1.1

Register Default Settings vs FS0, FS1........................................................................................19

5.1.2

A word ......................................................................................................................................20

5.1.3

B - word.......................................................................................................................................21

5.1.4

C - word.......................................................................................................................................22

5.1.5

D - word.......................................................................................................................................23

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 3 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Technical Data..........................................................................................................24

6.1 Absolute Maximum Ratings.............................................................................................. 24

6.2 Normal Operating Conditions ........................................................................................... 24

6.3 DC Characteristics ........................................................................................................... 25

6.4 AC System Characteristics of the Receiver Part .............................................................. 26

6.5 AC System Characteristics of the Transmitter Part .......................................................... 27

6.6 Serial Control Interface .................................................................................................... 27

6.7 Crystal Parameters .......................................................................................................... 27

Application Circuit Examples .................................................................................28

7.1 Programmable User Mode - FSK Application Circuit (internal AFC option) ...................... 28

7.2 Stand-alone User Mode - FSK Application Circuit ............................................................ 29

7.3 FSK test circuit component list (Fig. 12 and Fig. 13) ........................................................ 30

7.4 Programmable User Mode - FSK Application Circuit (external AFC option) ..................... 31

7.5 Stand-alone User Mode - FSK Application Circuit (external AFC option) ......................... 32

7.6 FSK (with external AFC) test circuit component list (Fig. 14 and Fig. 15)......................... 33

7.7 Programmable User Mode - ASK Application Circuit........................................................ 34

7.8 Stand-alone User Mode - ASK Application Circuit............................................................ 35

7.9 ASK test circuit component list (Fig. 16 and Fig. 17)........................................................ 36

Extended Frequency Range....................................................................................37

8.1 Board Component List (Fig. 18) ....................................................................................... 37

TX/RX Combining Network......................................................................................38

9.1 Board Component List (Fig. 19) ....................................................................................... 38

9.2 LNA input impedances in receive mode ........................................................................... 38

9.3 LNA input impedances in transmit mode.......................................................................... 38

9.4 PA load impedances ........................................................................................................ 38

10 Package Dimensions ...............................................................................................39

11 Reliability Information .............................................................................................40

12 ESD Precautions ......................................................................................................40

13 Disclaimer.................................................................................................................42

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 4 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Theory of Operation

1.1 General

The main building block of the transceiver is a programmable PLL frequency synthesizer that is based on an
integer-N topology. The PLL is used for generating the carrier frequency during transmission and for gener-
ating the LO signal during reception. The carrier frequency can be FSK-modulated by pulling the crystal and
ASK-modulated by on/off keying of the power amplifier. The receiver is based on the principle of a single
conversion superhet. Therefore the VCO frequency has to be changed between transmit and receive mode.
In receive mode, the preferred LO injection type is low-side injection.

The TH7120 transceiver IC consists of the following building blocks:

Low-noise amplifier (LNA) for high-sensitivity

RF signal reception with switchable gain

Mixer (MIX) for RF-to-IF down-conversion

IF amplifier (IFA) to amplify and limit the IF

signal and for RSSI generation

Phase-coincidence demodulator with external

ceramic discriminator (FSK Demodulator)

Operational amplifier, connected to demodula-

tor output (OA1)

Operational amplifier, integrator circuit for

external AFC mode (OA2)

Control logic with 3wire bus serial control inter-

face (SCI)

Reference oscillator (RO) with external crystal

Reference divider (R counter)

Programmable divider (N/A counter)

Phase-frequency detector (PFD)

Charge pump (CP)

Voltage controlled oscillator (VCO) with internal

varactor

Power amplifier (PA) with adjustable output

power

1.2 Technical Data Overview

Frequency range: 300 MHz to 930 MHz in

programmable user mode

Extended frequency range with external VCO

varactor diode: 27 MHz to 930 MHz

315 MHz, 433 MHz, 868 MHz or 915 MHz fixed-

frequency settings in stand-alone user mode

Power supply range: 2.2 V to 5.5 V

Temperature range: -40 °C to +85 °C

Standby current: 50 nA

Operating current: 7.5 mA in receive mode

at low gain

Operating current 12 mA in transmit mode

at -2 dBm output power

Adjustable output power range from 20 dBm

to +10 dBm

Sensitivity: -105 dBm at FSK with 150 kHz IF

filter BW

Sensitivity: -107 dBm at ASK with 150 kHz

IF filter BW

Maximum data rate: 40 kbit/s NRZ

Maximum input level: 10 dBm at FSK

and -20 dBm at ASK

Input frequency acceptance:

50 kHz (with

external AFC option)

Input frequency acceptance:

20 kHz (with

internal AFC option)

Frequency deviation range:

8 kHz to

80 kHz

Analog modulation frequency: max. 10 kHz

Crystal reference frequency: 3 MHz to 12 MHz

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 5 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

1.3 Block

Diagram

Fig. 1:

TH7120 block diagram

1.4 User Mode Features

The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled pro-
grammable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to fixed-
frequency mode the Stand-alone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be
connected to V

or V

in order to set the desired frequency of operation. The logic levels at pins FS0/SDEN

and FS1/LD must not be changed after power up in order to remain in fixed-frequency mode.
After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode
(PUM) while pin FS1/LD is now a PLL lock detector output. In this mode, the user can set any PLL frequency
or mode of operation by the SCI. In SUM pins FS0/SDEN and FS1/LD are used to set the desired frequency,
while in PUM pin FS0/SDEN is part of the 3-wire serial control interface (SCI) and pin FS1/LD is the look
detector output signal of the PLL synthesizer.

The following four fixed-frequency settings can be selected in SUM:

Channel frequency

433.92 MHz

868.3 MHz

315 MHz

915 MHz

Please refer to para. 4 for detailed information.

A mode control logic allows four different operational modes. In addition to standby, transmit and receive
mode, idle mode can be used to run only the reference oscillator and the PLL.
The different operational modes can be set in SUM and PUM as well. In SUM, the user can set the trans-
ceiver operational modes via control pins RE/SCLK and TE/SDTA, please refer to para. 4 for detailed infor-
mation.

The register bits OPMODE select the desired operation mode in PUM. It should be noted that the pin notifi-
cation RE/SCLK and TE/SDTA describes the modes Receive Enable and Transmit Enable in SUM. These
pins are part of the 3-wire SCI during PUM.

IN_LNA

LNA

I
N

_
L
N

_
M

I
X

OUT_DTA

OA2

bias

MIX

T
_
M

I
X
1

_
I
F
A

V
EE_

IFA

IN_DEM

_
I
F

OUT_DEM

OA1

INT1

INT2

RSSI

1.5pF

200k

L
N
A

MIX

Demodulator

FSK

VEE_PLL

OUT_PA

FSK

ASK

_
D
T
A

/
F
S
K

/
S
C

L
K

/
S
D
T
A

F
S
0
/
SD

PS_PA

_
S

1
/
LD

E
_
R
O

counter

L
K

T
A

Control Logic

SCI

VCO

VCC_PLL

TNK_LO

E
_
D
I
G

_
D

I
G

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 7 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Pin No.

Name

I/O Type

Functional Schematic

Description

VEE_RO

ground

ground of RO

analog I/O

36p

VEE

VCC

2.6µA

39k

36p

RO input, base of bipolar
transistor

FSK_SW

analog I/O

VCC

VEE

FSK_SW

FSK pulling pin, switch to
ground or OPEN

IN_DTA

input

ASK/FSK modulation data
input, pull down resistor
120k

RE/SCLK

input

receiver enable input / clock
input for the shift register,
pull down resistor 120k

TE/SDTA

input

VEE

VCC

IN_DTA

RE/SCLK

TE/SDTA

120k

120

transmitter enable input /
serial data input, pull down
resistor 120k

ASK/FSK

input

ASK/FSK mode select input

FS0/SDEN input

VEE

VCC

ASK/FSK

FS0/SDEN

120

frequency select input / se-
rial data enable input

VCC_DIG

supply

positive supply of serial port
and control logic

VEE_DIG

ground

ground of serial port and
control logic

FS1/LD

input

VEE

VCC

FS1/LD

120

frequency select input / lock
detector output

VCC_PLL

supply

positive supply of PLL fre-
quency synthesizer

VEE_PLL

ground

ground of PLL frequency
synthesizer

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 10 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Functional Description

3.1 PLL Frequency Synthesizer

The TH7120 contains an integer-N PLL frequency synthesizer. A PLL circuit performs the frequency synthe-
sis, via a feedback mechanism. The output frequency f

VCO

is generated as an integer multiple of the phase

detector comparison frequency f

.This reference frequency f

is generated by dividing the output frequency

of a crystal oscillator. The phase detector utilizes this signal as a reference to tune the VCO and in the

locked state it must be equal to the desired output frequency, divided by the feedback divider ratio N.

Fig. 2:

Integer-N PLL Frequency Synthesizer Topology

Thus, the output frequency the synthesizer generates can be set by programming the feedback divider.
Therefore the VCO can be tuned across the frequency band of interest. The only constraint to the frequency
output of the system is that the minimum frequency resolution, or minimum channel spacing, is equal to
f

with:

Where R is the reference divider factor.
When the PLL is in the unlocked state (e.g. during power up or during the reprogramming of a new feedback
divider ratio), the phase detector will create an error voltage proportional to the phase difference of the two
input signals. This error voltage is low-pass filtered by an external loop filter and will change the output fre-
quency of the VCO so that it satisfies the following equation:

VCO

There are four registers available to set different output frequencies in receive (registers RR and NR) and in
transmit mode (registers RT and NT). These registers can be programmed using the Serial Control Interface
in the Programmable User Mode (PUM). In case of Stand-alone User Mode (SUM), the registers are set fixed
values (refer to para. 4.1.1)

Reference

Oscillator

Reference

Divider

Feedback

Divider

Voltage Controlled

Oscillator

Phase-frequency

Detector

Charge

Pump

VCO

External

Loop Filter

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 11 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

3.1.1 Reference

Oscillator

The reference oscillator is based on a Colpitts topology with two
integrated functional capacitors as shown in figure 3. The circuitry
is optimized for a load capacitance range of 10 pF to 15 pF. The
equivalent input capacitance C

offered by the oscillator input pin

RO is about 18pF.
To ensure a fast and reliable start-up and a very stable frequency
over the specified supply voltage and temperature range, the os-
cillator bias circuitry provides an amplitude regulation. The ampli-
tude on pin RO is monitored in order to regulate the current of the
oscillator core I

. There are two limits ROMAX and ROMIN be-

tween the regulation is maintained. These values can be changed
via serial control interface in Programmable User Mode (PUM). In
Stand-alone User Mode (SUM), ROMAX and ROMIN are set to
default values (refer to para. 5.1.3). ROMAX defines the start-up
current of the oscillator. The ROMIN value sets the desired
steady-state current. If ROMIN is sufficient to achieve an ampli-
tude of about 400 mV on pin RO, the current I

will be set to

ROMIN. Otherwise the current will be permanently regulated be-
tween ROMIN and ROMAX. If ROMIN and ROMAX are equal, no
regulation takes place. For most of the applications ROMIN and
ROMAX should not be changed from default.

Fig. 3:

Reference oscillator circuit

3.1.2 Reference

Divider

The reference divider provides the input signal of the phase detector by dividing the signal of the reference
oscillator. The ratio of the reference divider ranged is

1023

3.1.3 Feedback

Divider

The feedback divider of the PLL is based on a pulse-swallow topology. It contains a 4-bit swallow A-counter,
a 13-bit program B-counter and a prescaler. The divider ratio of the prescaler is controlled by the program
counter and the swallow counter. During one cycle, the prescaler divides by 17 until the swallow A-counter
reaches its terminal count. Afterwards the prescaler divides by 16 until the program counter reaches its ter-
minal count. Therefore the overall feedback divider ratio can be expressed as:

(

)

The A-counter configuration represents the lower bits in the feedback divider register (N

0-3

= A

0-3

) and the

upper bits the B-counter configuration (N

4-16

= B

0-12

) respectively. According to that, the following counter

ranges are implemented:

;

8191

and therefore the range of the overall feedback divider ratio results in:

131071

The user does not need to care about the A- and B-counter settings. It is only necessary to know the overall
feedback divider ratio N to program the register settings.

36pF

XTAL

FSKSW

CX2

CX1

VCC

36pF

VEE

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 12 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

3.1.4 Phase-frequency

Detector

The phase detector creates an error voltage proportional to the phase difference between the reference sig-
nal f

and f

. The implementation of the phase detector is a phase-frequency type. That circuitry is very useful

because it decreases the acquisition time significantly. The gain of the phase detector can be expressed as:

where I

is the charge pump current which is set via register CPCUR. In the TH7120 design the VCO fre-

quency control characteristic is with negative polarity. This means the VCO frequency increases if the loop
filter output voltage decreases and vice versa. In case an external varactor diode is added to the VCO tank,
the tuning characteristic can be changed between positive and negative depending on the particular varactor
diode circuitry. Therefore the PDFPOL register can be used to define the phase detector polarity.

3.1.5 Lock

Detector

In Programmable User Mode a lock-detect signal LD is available at pin FS1/LD (pin 19). The lock detection
circuitry uses Up and Down signals from the phase detector to check them for phase coherency. Figure 4
shows an overview of the lock signal generation. The locked state and the unlock condition will be decided on
the register settings of LDTM and ERTM respectively. In the start-up phase of the PLL, Up and Down signals
are quite unbalanced and counter CNT_LD receives no clock signal. When the loop approaches steady state,
the signals Up and Down begin to overlap and CNT_LD counts down. Herein register LDTM sets the number
of counts which are necessary to set the lock detection signal LD. If an unlock condition occurs, the counter
CNT_LD will be reloaded and therefore its CARRY falls back.

Fig. 4:

Lock Detection Circuit

The CNT_ER supervises the unlock condition. If Up and Down are consecutive, the counter CNT_ER will be
reloaded permanently and its CARRY will not be set, otherwise the counter level of CNT_ER will be reduced
by the reference oscillator clock (1/f

). The register ERTM decides on the maximum number of clocks dur-

ing Up and Down signals can be non-consecutive without loosing the locked state.
The transceiver offers two ways of analyzing the locked state. If the register LOCKMODE is set to `0', only
one occurrence of the locked state condition is needed to remain LD = 1 during the whole active mode, oth-
erwise the state of the PLL will be observed permanently.

RESET LD

Control

Logic

CNT_LD

CARRY

LOAD

Down

PFD

LDTM [1 : 0]

LOCKMODE

ERTM [1 : 0]

CNT_ER

CARRY

LOAD

MUX

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 13 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

3.1.6 Voltage Controlled Oscillator with external Loop Filter

The transceiver provides a LC-based voltage-controlled oscillator with an
external inductance element connected between VCC and pin TNK_LO.
An internal varactor diode in series with a fixed capacitor forms the vari-
able part of the oscillator tank. The oscillation frequency is adjusted by the
DC-voltage at pin LF. The tuning sensitivity of the VCO is approximately
20MHz/V for 433MHz operations and 40MHz/V at 868MHz. Since the
internal varactor is connected to VCC, a lower voltage on pin LF causes
the capacitance to decrease and the VCO frequency to increase. For this
reason the phase detector polarity should be negative (PFDPOL = 0). If
the operation frequency is below 300MHz, an external varactor diode
between pin TNK_LO and VCC_PLL is necessary. The corresponding
application schematic is shown in section 8. The VCO current VCOCUR
can be adjusted via serial control interface in order to ensure stable os-
cillations over the whole frequency range.

Fig. 5:

VCO schematic

3.1.7 Loop

Filter

Since the loop filter has a strong impact on the function of the PLL, it must
be chosen carefully. For FSK operation the bandwidth of the loop filter
must be selected wide enough for a fast relock of the PLL during crystal
pulling. Also the bandwidth should be wider than the rate of the data bit
stream. In case of ASK or OOK modulation the bandwidth can be smaller
since the operating frequency will not be changed. The suggested filter
topology is shown in Fig. 6. The dimensions of the loop filter elements can
be derived using well known formulas in application notes and other ref-
erence literature.

Fig. 6:

order Loop filter

3.2 Receiver

Part

The RF front-end of the receiver part is a heterodyne configuration that converts the input radio-frequency
(RF) signal into an intermediate frequency (IF) signal. The most commonly used IF frequency is 10.7 MHz,
but IF frequencies in the range of 455 kHz to 20.4 MHz can also be used. According to the block diagram, the
front-end consists of a LNA, a Mixer and an IF limiting amplifier with received signal strength indicator (RSSI).
The local oscillator (LO) signal for the mixer is generated by the PLL frequency synthesizer.

3.2.1 LNA

The LNA is based on a cascode topology for low-noise, high gain and good reverse isolation. The open col-
lector output has to be connected two an external resonance circuit which is tuned to the receive frequency.
The gain of the LNA can be changed in order to achieve a high dynamic range. There are two possibilities for
the gain setting which can be selected by the register bit LNACTRL. External control can be done via the pin
GAIN_LNA, internal control is given by the register bit LNAGAIN. In case of external gain control, a hysteresis
of about 340 mV can be chosen via the register bit LNAHYST. This configuration is useful if an automatic
gain control loop via the RSSI signal is established. In transmit mode the LNA-input is shorted to protect the
amplifier from saturation and damaging.

3.2.2 Mixer

The mixer is a double-balanced mixer which downconverts the receive frequency to the IF frequency. The
preferred LO injection type is low side. The output of the mixer is about 330Ohm in order to match the IF
channel selection filter.

VCO

CF1

CF2

RF1

VEE

Charge Pump

6.3pF

External

Loop Filter

VCC

TNK_LO

VCOCUR

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 14 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

3.2.3 IF

Amplifier

After passing the channel select filter which sets the IF bandwidth the signal is limited by means of an high
gain limiting amplifier. The small signal gain is about 80 dB. The RSSI signal is generated within the IF ampli-
fier. The output of the RSSI signal is available at pin RSSI. The voltage at this pin is proportional to the input
power of the receiver in dBm. Using this RSSI output signal the signal strength of different transmitters can
be distinguished.

3.2.4 ASK

Demodulator

The RSSI signal is also used for ASK reception. ASK demodulation is done by means of adaptive threshold
slicing. Therefore the OA1 is used. The capacitor at pin RSSI smoothes the RSSI signal and the capacitor at
pin INT1 adjusts the data filter corner frequency f

according to

200

This value has to be matched according to the desired data rate.

3.2.5 FSK

Demodulator

The implemented FSK demodulator is based on the phase-coincidence principle. A 90-degree phase shifter,
which can either consists of a ceramic resonator or an LC tank, is connected to pin IN_DEM.

3.3 Transmitter

Part

The output of the PLL frequency synthesizer feeds a power amplifier (PA) in order to setup a complete RF
transmitter. The VCO frequency is identical to the carrier frequency.

3.3.1 Power

Amplifier

The power amplifier (PA) has been designed to deliver up to 10 dBm in the specified frequency bands. The
power amplifier output pin OUT_PA is an open collector output. Naturally, the greater the output voltage
swing can be the better the power efficiency will be. The PA must be matched to deliver the best efficiency in
terms of output power and current consumption.

3.3.2 Output Power Adjustment

The output power can be adjusted via the
external resistor RPS. The relationship be-
tween the output power and RPS is shown in
Figure 7. There are four predefined attenua-
tion steps available in programmable user
mode which are selected by the register
TXPOWER. Herein the output power can be
reduced from 6 dB to 20 dB. In stand-alone
user mode the attenuation is 0 dB.

Fig. 7:

Output power vs. RPS

100

RPS / kOhm

-40,00

-30,00

-20,00

-10,00

0,00

10,00

20,00

/ dB

315MHz
433MHz
868MHz
915MHz

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 15 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

3.3.3 Modulation

Schemes

The RF carrier generated by the PLL frequency synthesizer can be ASK or FSK modulated. In dependency
on the selected user mode the modulation type can be either selected by the ASK/FSK pin or via the serial
control interface. The input data has always to be applied at the pin IN_DTA.

3.3.4 ASK

Modulation

IN_DTA

Description

Power amplifier is turned off

Power amplifier is turned on

(according to the selected output power)

The transceiver can be ASK-modula-
ted by turning-on and -off the power
amplifier and therefore it leads to an
ASK signal at the output.

3.3.5 FSK

Modulation

FSK modulation can be achieved by pulling the crystal oscillator
frequency. A CMOS-compatible data stream applied at the pin
IN_DTA digitally modulates the XOSC via an integrated NMOS
switch. Two external pulling capacitors CX1 and CX2 allow the
FSK deviation

f and center frequency f

to be adjusted inde-

pendently. At IN_DTA = Low CX2 is connected in parallel to CX1
leading to the low-frequency component of the FSK spectrum
(f

min

); while at IN_DTA = High CX2 is deactivated and the XOSC is

set to its high frequency, leading to f

max

IN_DTA

Description

min

= f

f (FSK switch is closed)

max

= f

f (FSK switch is open)

An external reference signal can be directly AC-coupled to the
reference oscillator input pin RO. Then the transceiver is used
without a XTAL. Now the reference signal sets the carrier fre-
quency and has to contain the FSK (or FM) modulation.

Fig. 8:

Crystal Pulling Circuit

3.3.6 Crystal

Pulling

A crystal is tuned by the manufacturer to the re-
quested oscillation frequency f

for a certain load

capacitance CL within the specified calibration
tolerance. The only way to tune this oscillation fre-
quency is to vary the effective load capacitance
CL

eff

seen by the crystal.

Figure 8 shows the oscillation frequency of a crys-
tal in dependency on the effective load capaci-
tance. This capacitance changes in accordance
with the logic level of IN_DTA around the specified
load capacitance. The figure illustrates the relation-
ship between the external pulling capacitors and
the frequency deviation.

Fig. 9:

Crystal Pulling Characteristic

36pF

XTAL

FSKSW

CX2

CX1

VCC

36pF

VEE

min

max

eff

XTAL

CX1 CRO
CX1+CRO

(CX1+CX2) CRO

CX1+CX2+CRO

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 16 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Description of User Modes

4.1 Stand-alone User Mode Operation

After power up the transceiver is set to stand-alone user mode. In this mode, pins FS0/SDEN and FS1/LD
must be connected to V

or V

to set the desired frequency of operation. The logic levels at pins FS0/SDEN

and FS1/LD must not be changed after power up in order to remain in stand-alone user mode. The default
settings of the control word bits in stand-alone user mode are described in the frequency selection table.

4.1.1 Frequency

Selection

Channel frequency

433.92 MHz

868.3 MHz

315 MHz

915 MHz

FS0/SDEN

FS1/LD

Reference oscillator frequency

7.1505 MHz

R counter ratio in RX mode

PFD frequency in RX mode

446.91 kHz

397.25 kHz

238.35 kHz

N/A counter ratio in RX mode

947

1919

766

3794

VCO frequency in RX mode

423.22 MHz

857.60 MHz

304.30 MHz

904.30 MHz

RX frequency

433.92 MHz

868.30 MHz

315.00 MHz

915.00 MHz

R counter ratio in TX mode

PFD frequency in TX mode

446.91 kHz

397.25 kHz

238.35 kHz

N/A counter ratio in TX mode

971

1943

793

3839

VCO frequency in TX mode

433.92 MHz

868.30 MHz

315.00 MHz

915.00 MHz

TX frequency

433.92 MHz

868.30 MHz

315.00 MHz

915.00 MHz

IF in RX mode

10.7 MHz

In the stand-alone user mode, the transceiver can be set the to Standby, Receive, Transmit or Idle (only PLL
synthesizer active) mode via control pins RE/SCLK and TE/SDTA.

Operation mode

Standby

Receive

Transmit

Idle

RE/SCLK

TE/SDTA

Note: Pins with internal pull-down

In this mode, the modulation type selection can be done via pin ASK/FSK

Modulation type

ASK

FSK

ASK / FSK

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 17 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

4.2 Programmable User Mode Operation

The transceiver can also be used in the programmable user mode. After power-up the first logic change at
pin FS0/SDEN enters into this mode. Now the full functionality is accessable via the Serial Control Interface
(SCI).

4.2.1 Serial Control Interface Description

A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in program-
mable user mode. At each rising edge of the SCLK signal, the logic value on the SDTA pin is written into a
24-bit shift register. The data stored in the shift register are loaded into one of the 4 appropriate latches on
the rising edge of SDEN. The control words are 24 bits lengths: 2 address bits and 22 data bits. The first two
bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least significant 24
bits are serial-clocked into the shift register. The first incoming bit is the most significant bit (MSB). To pro-
gram the transceiver in multi-channel application, four 24-bit words may be sent: A-word, B-word, C-word and
D-word. If individual bits within a word have to be changed, then it is sufficient to program only the appropriate
24-bit word. The serial data input timing and the structure of the control words are illustrated in Fig. 10 and

Fig. 10: SCI Block Diagram

Due to the static CMOS design, the SCI consumes virtually no current and it can be programmed in active as
well as in standby mode.

Fig. 11: Serial Data Input Timing

CWH

CWL

bit 22

bit 1

bit 0

bit 23

data

Invalid

LSB

MSB

SDTA

SCLK

SDEN

data

Invalid

A - LATCH

ADDR DECODER

B - LATCH

C - LATCH

D - LATCH

A-word

` '

B-word

D-word

C-word

24-BIT

SHIFT REGISTER

SDEN

SDTA

SCLK

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 18 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Register Description

As shown in the previous section there are four control words which stipulates the operation of the whole
chip. In Stand-alone User Mode SUM the intrinsic default values with respect to the applied levels at pins FS0
and FS1 lay down the configuration of the transceiver. In Programmable User Mode PUM the register set-
tings can be changed via 3-wire interface SCI. The following table depicts an overview of the register configu-
ration of the TH7120.

5.1 Register

Overview

WORD

DATA

MSB

LSB

23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bit No.

Depends on FS0/FS1 voltage level after power up

default

Set to 0

POL

DSEL

CPCUR

LOCKM

ODE

CTRL

TXPOWER

[ 1 :

]

Set to 1

OPM

[ 1 :

0 ]

[ 9 :

0 ]

23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bit No.

Depends on FS0/FS1 voltage level after power up

default

Set to 0

Set to 1

DELPLL

LNA

YST

Set to 0

ROM

[ 2 :

0 ]

ROM

I
N

[ 2 :

0 ]

[ 9 :

0 ]

23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bit No.

Depends on FS0/FS1 voltage level after power up

default

LNA

TRL

PFDPOL

VCOCUR

[ 1 :

]

[ 16 :

0 ]

23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bit No.

Depends on FS0/FS1 voltage level after power up

default

DCTRL

LDTM

[ 1 :

]

ERTM

[ 1 :

]

[ 16 :

0 ]

The default settings which vary with the desired working frequency depend on the voltage levels at the fre-
quency selection pins FS0 and FS1. The next table shows the default register settings of different frequency
selections. It should be noted that the channel frequency listed below will be achieved with a crystal frequency
of 7.1505 MHz.

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 20 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

5.1.2 A word

Name

Bits

Description

Reference divider ratio in RX operation mode

[9:0]

4d .. 1023d

Operation mode

OPMODE

[11:10]

00
01
10
11

Standby mode
Receive mode
Transmit mode
Idle mode

#default

LNA gain

0
1

low LNA gain
high LNA gain

#default

LNAGAIN

[12]

This selection is valid if bit LNACTR (bit 21 in C-word) is set to internal LNA gain control.

not used

[13]

set to `1' for correct function

Output power attenuation

00
01
10
11

-
-
-
-

20 dB

-
-
-
-

12 dB

-
-
-
-

6 dB

#default

TXPOWER

[15:14]

The power selection resistor R

connected between pin PS_PA and ground selects the

output power P

Set the PA-on condition

PACTRL

[16]

0
1

PA is switched on if the PLL locks
PA is always on in TX mode

#default

Set the PLL locked state observation mode

before lock only

#default

Locked state condition will be ascertained only one time afterwards the LD signal remains
in high state.

before and after lock

LOCKMODE

[17]

locked state will be observed permanently

Charge Pump output current

CPCUR

[18]

0
1

±
±
±
±

260 µA

±
±
±
±

1300 µA

#default

Modulation mode

0
1

ASK
FSK

#default

MODSEL

[19]

This selection is valid if bit MODCTRL (bit 21 in D-word) is set to internal modulation
control.

Input data polarity

Normal

#default

`0' for space at ASK or f

min

at FSK, `1' for mark at ASK or f

max

at FSK

Inverse

DTAPOL

[20]

`1' for space at ASK or f

min

at FSK, `0' for mark at ASK or f

max

at FSK

not used

[21]

set to `0' for correct function

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 21 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

5.1.3 B - word

Name

Bits

Description

Reference divider ratio in RX operation mode

[16:0]

4d .. 1023d

Set the desired steady state current of the reference oscillator

ROMIN

[12:10]

000
001
010
011
100
101
110
111

µ
µ
µ
µ

100

µ
µ
µ
µ

150

µ
µ
µ
µ

A #default

200

µ
µ
µ
µ

250

µ
µ
µ
µ

300

µ
µ
µ
µ

350

µ
µ
µ
µ

The control circuitry regulates the current of the oscillator core
between the values ROMAX and ROMIN. As the regulation in-
put signal the amplitude on pin RO is used. If the ROMIN value
is sufficient to achieve an amplitude of about 400mV on pin RO
the current of the reference oscillator core will be set to ROMIN.
Otherwise the current will be permanently regulated between
ROMAX and ROMIN. If ROMIN and ROMAX are equal no
regulation of the oscillator current occurs. Please also note the
block description of the reference oscillator in para. 3.1.1..

Set the start-up current of the reference oscillator

ROMAX

[15:13]

000
001
010
011
100
101
110
111

µ
µ
µ
µ

100

µ
µ
µ
µ

150

µ
µ
µ
µ

200

µ
µ
µ
µ

250

µ
µ
µ
µ

300

µ
µ
µ
µ

350

µ
µ
µ
µ

A #default

Set the start-up current of the reference oscillator core. Please
also note the description of the ROMIN register and the block
description of the reference oscillator which can be seen above.

not used

[16]

set to `0' for correct function

Internal AFC feature

0
1

disabled
enabled

#default

AFC

[17]

If this feature is enabled, the acceptance range in receive mode will be increased to appr.

20kHz.

Hysteresis on pin GAIN_LNA

LNAHYST

[18]

0
1

disabled
enabled - typical 340 mV (V

= 1.56V, V

= 1.22V)

#default

Delayed start of the PLL

undelayed start

PLL starts at the reference oscillator start-up

delayed start

#default

DELPLL

[19]

PLL starts

500

s after entering an active mode to ensure reliable oscillation of the refer-

ence oscillator.

not used

[20]

set to `1' for correct function

not used

[21]

set to `0' for correct function

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 24 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Technical Data

6.1 Absolute Maximum Ratings

Parameter

Symbol

Condition / Note

Min

Max

Unit

Supply voltage

7.0

Input voltage

- 0.3

+0.3

Input RF level

iRF

@ LNA input

dBm

Power dissipation

diss

0.25

Storage temperature

STG

-40

+125

°C

Junction temperature

+125

°C

Electrostatic discharge

ESD1

human body model, 1)

-1.0

+1.0

Electrostatic discharge

ESD2

human body model, 2)

TBD

1) pins IN_DTA, ASK/FSK, RE/SCLK; TE/SDTA, FS0/SDEN, FS1/LD
2) all pins, except IN_DTA, ASK/FSK, RE/SCLK; TE/SDTA, FS0/SDEN, FS1/LD

6.2 Normal Operating Conditions

Parameter

Symbol

Condition

Min

Max

Unit

Supply voltage

2.2

5.5

Operating temperature

-40

+85

ºC

Input low voltage (CMOS)

IN_DTA, RE/SCLK,
TE/SDTA, ASK/FSK,
FS0/SDEN, FS1/LD

pins

0.3*V

Input high voltage (CMOS)

IN_DTA, RE/SCLK,
TE/SDTA, ASK/FSK,
FS0/SDEN, FS1/LD

pins

0.7*V

Transmit frequency range

300

930

MHz

Receive frequency range

300

930

MHz

VCO frequency

VCO

Set by tank configuration

300

930

MHz

IF range

- f

VCO

0.4

MHz

RO frequency

Set by crystal

MHz

PFD working frequency

PFD

Set by crystal and
R-counter

0.01

MHz

Frequency deviation

at FM or FSK

kHz

FSK data rate

FSK

NRZ

kbit/s

ASK data rate

ASK

NRZ

kbit/s

FM bandwidth

kHz

= 433.92MHz

VCO gain

= 868.3MHz

VCO

MHz/V

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 25 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

6.3 DC

Characteristics

all parameters under normal operating conditions, unless otherwise stated;
typical values at T

= 23 °C and V

= 3 V

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Standby current

SBY

mode = standby

100

Band bit
0 (< 500 MHz)

3.8

4.4

Idle current

1 (> 500 MHz)

IDLE

mode = idle

6.7

7.7

0 (< 500 MHz)

6.9

8.0

1 (> 500 MHz)

RXL_ASK

mode = receive, ASK
LNA @ low gain

9.9

11.4

0 (< 500 MHz)

8.2

9.4

Receive supply
current - ASK

1 (> 500 MHz)

RXH_ASK

mode = receive, ASK
LNA @ high gain

11.2

12.9

0 (< 500 MHz)

7.7

8.9

1 (> 500 MHz)

RXL_FSK

mode = receive, FSK
LNA @ low gain

10.7

12.3

0 (< 500 MHz)

9.0

10.4

Receive supply
current - FSK

1 (> 500 MHz)

RXH_FSK

mode = receive, FSK
LNA @ high gain

13.8

0 (< 500 MHz)

11.5

13.2

Transmit
supply current
@ P

max

20 dB

1 (> 500 MHz)

TX_00

Mode = transmit,
RPS = see para. 7.3
TXPOWER = 00

15.5

17.8

0 (< 500 MHz)

12.2

Transmit
supply current
@ P

max

12 dB

1 (> 500 MHz)

TX_01

Mode = transmit,
RPS = see para. 7.3
TXPOWER = 01

16.4

18.9

0 (< 500 MHz)

16.1

Transmit
supply current
@ P

max

6 dB

1 (> 500 MHz)

TX_10

Mode = transmit,
RPS = see para. 7.3
TXPOWER = 10

17.5

20.1

0 (< 500 MHz)

Transmit
supply current
@ P

max

1 (> 500 MHz)

TX_11

Mode = transmit,
RPS = see para. 7.3
TXPOWER = 11

27.6

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 26 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

6.4 AC System Characteristics of the Receiver Part

all parameters under normal operating conditions, unless otherwise stated; all parameters based on test
circuits for FSK (Fig. 12 to 15) and ASK (Fig. 16 to 17), respectively;

Parameter

Symbol

Condition

Min

Typ

Max

Unit

= 433.92MHz

-96

dBm

= 868.3MHz

minL_ASK

= 150kHz, f

= 2kHz

BER

-3

LNA @ low gain

-96

dBm

= 433.92MHz

-107

dBm

Input sensitivity
ASK

= 868.3MHz

minH_ASK

= 150kHz, f

= 2kHz

BER

-3

LNA @ high gain

-107

dBm

= 433.92MHz

-87

dBm

= 868.3MHz

minL_ASK

= 150kHz, f

= 2kHz

f =

50 kHz

BER

-3

LNA @ low gain

-87

dBm

= 433.92MHz

-105

dBm

Input sensitivity
FSK

= 868.3MHz

minH_ASK

= 150kHz, f

= 2kHz

f =

50 kHz

BER

-3

LNA @ high gain

-105

dBm

= 433.92MHz

-10

dBm

= 868.3MHz

maxL_ASK

= 150kHz, f

= 2kHz

BER

-3

LNA @ low gain

-10

dBm

= 433.92MHz

-20

dBm

Maximum input
signal
ASK

= 868.3MHz

maxH_ASK

= 150kHz, f

= 2kHz

BER

-3

LNA @ high gain

-20

dBm

= 433.92MHz

-10

dBm

= 868.3MHz

maxL_FSK

= 150kHz, f

= 2kHz

BER

-3

LNA @ low gain

-10

dBm

= 433.92MHz

-20

dBm

Maximum input
signal
FSK

= 868.3MHz

maxH_FSK

= 150kHz, f

= 2kHz

BER

-3

LNA @ high gain

-20

dBm

Start-up time - ASK

on_ASK

from standby to receive
mode

2.5

Start-up time - FSK

on_FSK

from standby to receive
mode

2.5

Spurious emission

spur_RX

referred to receiver
input

-54

dBm

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 27 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

6.5 AC System Characteristics of the Transmitter Part

all parameters under normal operating conditions, unless otherwise stated;
typical values at T

= 23 °C and V

= 3 V;

all parameters based on test circuits for FSK (Fig. 12 to 15), FM and ASK (Fig. 16 to 17), respectively;

Parameter

Symbol

Condition

Min

Typ

Max

Unit

= 433.92MHz

-10

dBm

Output power
@ P

max

20 dB

= 868.3MHz

TX_00

mode = transmit,
RPS = see para. 7.3
TXPOWER = 00

-14

dBm

= 433.92MHz

-2

dBm

Output power
@ P

max

12 dB

= 868.3MHz

TX_01

mode = transmit,
RPS = see para. 7.3
TXPOWER = 01

-6

dBm

= 433.92MHz

dBm

Output power
@ P

max

6 dB

= 868.3MHz

TX_10

mode = transmit,
RPS = see para. 7.3
TXPOWER = 10

-1

dBm

= 433.92MHz

dBm

Output power
@ P

max

= 868.3MHz

TX_11

mode = transmit,
RPS = see para. 7.3
TXPOWER = 11

dBm

FSK deviation

FSK

depends on C

, C

and

crystal parameter

kHz

FM deviation

adjustable with varactor
and V

kHz

Modulation frequency FM

mod

kHz

PLL reference spurious emission P

spur_PLL

-40

dBm

Harmonic emission

harm

-36

dBm

Star-up time

on_TX

From standby to
transmit mode

2.5

6.6 Serial Control Interface

Parameter

Symbol

Condition

Min

Max

Unit

Data to clock set up time

150

Data to clock hold time

Clock pulse width high

CWH

100

Clock pulse width low

CWL

100

Clock to load enable set
up time

100

6.7 Crystal

Parameters

Parameter

Symbol

Condition

Min

Max

Unit

Crystal frequency

crystal

fundamental mode, AT

MHz

Load capacitance

load

Static capacitance

Series resistance

Spurious response

spur

only required for FSK modulation

-10

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 30 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

7.3 FSK test circuit component list (Fig. 12 and Fig. 13)

Part

Size

Value @

315 MHz

Value @

433.92 MHz

Value @

868.3 MHz

Value @

915 MHz

Tol.

Description

0603

5.6 pF

NIP

LNA output tank capacitor

0603

4.7 pF

1 pF

1.5 pF

MIX input matching capacitor

0805

10 nF

10% data slicer capacitor

0805

330 pF

10% demodulator output low-pass

capacitor, depending on data rate

0805

1.5 nF

10% RSSI output low pass capacitor

CB0

0805

100 nF

10% blocking capacitor

CB1

0603

330 pF

10% blocking capacitor

CB2

0805

330 pF

10% blocking capacitor

CB4

0805

330 pF

10% blocking capacitor

CB5

0603

330 pF

10% blocking capacitor

CB6

0603

330 pF

47 pF

10% blocking capacitor

CB7

0603

330 pF

10% blocking capacitor

CF1

0805

330 pF

loop filter capacitor

CF2

0805

150 pF

loop filter capacitor

CX1

0805

18 pF

22 pF

RO capacitor for FSK (

f =

20 kHz)

CX2

0805

150 pF

27 pF

39 pF

RO capacitor for FSK (

f =

20 kHz)

CP0

0805

10 - 12 pF

CERRES tuning capacitor

CRX0

0603

100 pF

RX coupling capacitor

CTX0

0603

3.3 pF

2.2 pF

TX coupling capacitor

0603

10 K

CERRES loading resistor

0805

62 k

56 k

loop filter resistor

RPS

0805

27 k

33 k

47 k

62 k

power-select resistor

0805

47 nH

27 nH

3.3 nH

2.2 nH

VCO tank inductor

0603

27 nH

15 nH

10 nH

LNA output tank inductor

LTX0

0805

68 nH

220 nH

82 nH

TX impedance matching inductor

XTAL

HC49

SMD

7.1505 MHz

30ppm calibrate,

30ppm temperature

fundamental-mode crystal,
C

load

= 10 pF to 15pF, C

0, max

= 7 pF,

m, max

= 70

CERFIL

Leaded

type

SFE10.7MFP

@ B

IF2

= 40 kHz

ceramic filter from Murata (optional
for narrow band applications)

SMD

type

SFECV10.7MJS-A

@ B

IF2

= 150 kHz,

40kHz

ceramic filter from Murata

CERRES

SMD

type

CDACV10.7MG18-A

ceramic resonator from Murata

Notes:

NIP not in place, may be used optionally

Antenna matching network according to Evaluation Board Description EVB7120

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 31 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

7.4 Programmable User Mode - FSK Application Circuit (external AFC option)

Fig. 14: Test circuit in Programmable User Mode for FSK operation with external AFC

Circuit Features

Automatic Frequency Control (AFC)

Increases input frequency acceptance range up to RF

nom

50 kHz

Compensation of calibration tolerances of ceramic resonator

Compensation of temperature tolerances of ceramic resonator

VCC

Lock

detect

FSK

output

FSK

input

CX1

CX2

CERFIL

XTAL

CTX0

LTX0

CRX0

RSSI

OUT_MIX

CERRES

CB5

CB0

CB1

CB2

CB7

RE/SCLK

IN_DTA

ASK/FSK

FSK_SW

VEE_RO

VCC_DIG

VEE_

I
G

_LO

OUT_PA

IN_LNA

OUT_LNA

VEE_IF

GAIN_LNA

IN_MIX

VEE_LNA

I
F

SSI

T
A

CC_

VCC

/
SD

CB4

RF input

RF output

RPS

CF1

CF2

RF CB6

SCLK

SDTA

SDEN

3wire bus

-Controller

Antenna

matching

network

TH7120

CP1

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 32 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

7.5 Stand-alone User Mode - FSK Application Circuit (external AFC option)

Fig. 15: Test circuit in Stand-alone User Mode for FSK operation with external AFC

Circuit Features

Automatic Frequency Control (AFC)

Increases input frequency acceptance range up to RF

nom

50 kHz

Compensation of calibration tolerances of ceramic resonator

Compensation of temperature tolerances of ceramic resonator

FSK

output

FSK

input

enable

CX1

CX2

CERFIL

XTAL

CTX0

LTX0

CRX0

RSSI

/
SD

OUT_MIX

CERRES

CB5

CB0

CB1

CB2

CB7

RE/SCLK

IN_DTA

ASK/FSK

FSK_SW

_LO

OUT_PA

IN_LNA

OUT_LNA

GAIN_LNA

IN_MIX

I
F

SSI

T
A

VCC

CB4

RF input

RF output

CX2

RF input

RF output

VCC

RPS

CF1

CF2

RF CB6

CP1

VCC_DIG

I
F

VEE_

I
G

VEE_LNA

VEE_IF

VEE_RO

see para. 4.1.1

TH7120

Antenna

matching

network

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 33 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

7.6 FSK (with external AFC) test circuit component list (Fig. 14 and Fig. 15)

Part

Size

Value @

315 MHz

Value @

433.92 MHz

Value @

868.3 MHz

Value @

915 MHz

Tol.

Description

0603

5.6 pF

NIP

LNA output tank capacitor

0603

4.7 pF

1 pF

1.5 pF

MIX input matching capacitor

0805

10 nF

10% data slicer capacitor

0805

330 pF

10% demodulator output low-pass

capacitor, depending on data rate

0805

1.5 nF

10% RSSI output low pass capacitor

CB0

0805

100 nF

10% blocking capacitor

CB1

0603

330 pF

10% blocking capacitor

CB2

0805

330 pF

10% blocking capacitor

CB4

0805

330 pF

10% blocking capacitor

CB5

0603

330 pF

10% blocking capacitor

CB6

0603

330 pF

47 pF

10% blocking capacitor

CB7

0603

330 pF

10% blocking capacitor

CF1

0805

330 pF

loop filter capacitor

CF2

0805

150 pF

loop filter capacitor

CX1

0805

18 pF

22 pF

RO capacitor for FSK (

f =

20 kHz)

CX2

0805

150 pF

27 pF

39 pF

RO capacitor for FSK (

f =

20 kHz)

CP1

0805

33 pF

CERRES loading capacitor

CRX0

0603

100 pF

RX coupling capacitor

CTX0

0603

3.3 pF

2.2 pF

TX coupling capacitor

0603

10 K

CERRES loading resistor

0805

100 K

varactor diode biasing resistor

0805

62 k

56 k

loop filter resistor

RPS

0805

27 k

33 k

47 k

62 k

power-select resistor

0805

47 nH

27 nH

3.3 nH

2.2 nH

VCO tank inductor

0603

27 nH

15 nH

10 nH

LNA output tank inductor

LTX0

0805

68 nH

220 nH

82 nH

TX impedance matching inductor

SOD-323

BB535

varactor diode from Infineon

XTAL

HC49

SMD

7.1505 MHz

30ppm calibrate,

30ppm temperature

fundamental-mode crystal,
C

load

= 10 pF to 15pF, C

0, max

= 7 pF,

m, max

= 70

CERFIL

Leaded

type

SFE10.7MFP

@ B

IF2

= 40 kHz

ceramic filter from Murata (optional
for narrow band applications)

SMD

type

SFECV10.7MJS-A

@ B

IF2

= 150 kHz,

40kHz

ceramic filter from Murata

CERRES

SMD

type

CDACV10.7MG18-A

ceramic resonator from Murata

Notes:

NIP not in place, may be used optionally

Antenna matching network according to Evaluation Board Description EVB7120

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 36 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

7.9 ASK test circuit component list (Fig. 16 and Fig. 17)

Part

Size

Value @

315 MHz

Value @

433.92 MHz

Value @

868.3 MHz

Value @

915 MHz

Tol.

Description

0603

5.6 pF

NIP

LNA output tank capacitor

0603

4.7 pF

1 pF

1.5 pF

MIX input matching capacitor

0805

10 nF

10% data slicer capacitor

0805

1.5 nF

10% RSSI output low pass capacitor

CB0

0805

100 nF

10% blocking capacitor

CB1

0603

330 pF

10% blocking capacitor

CB2

0805

330 pF

10% blocking capacitor

CB5

0603

330 pF

10% blocking capacitor

CB6

0603

330 pF

47 pF

10% blocking capacitor

CB7

0603

330 pF

10% blocking capacitor

CF1

0805

330 pF

loop filter capacitor

CF2

0805

150 pF

loop filter capacitor

CX1

0805

18 pF

22 pF

RO capacitor

CRX0

0603

100 pF

RX coupling capacitor

CTX0

0603

3.3 pF

2.2 pF

TX coupling capacitor

0805

62 k

56 k

loop filter resistor

RPS

0805

27 k

33 k

47 k

62 k

power-select resistor

0805

47 nH

27 nH

3.3 nH

2.2 nH

VCO tank inductor

0603

27 nH

15 nH

10 nH

LNA output tank inductor

LTX0

0805

68 nH

220 nH

82 nH

TX impedance matching inductor

XTAL

HC49

SMD

7.1505 MHz

30ppm calibrate,

30ppm temperature

fundamental-mode crystal,
C

load

= 10 pF to 15pF, C

0, max

= 7 pF,

m, max

= 70

CERFIL

Leaded

type

SFE10.7MFP

@ B

IF2

= 40 kHz

ceramic filter from Murata (optional
for narrow band applications)

SMD

type

SFECV10.7MJS-A

@ B

IF2

= 150 kHz,

40kHz

ceramic filter from Murata

Notes:

NIP not in place, may be used optionally

Antenna matching network according to Evaluation Board Description EVB7120

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 37 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Extended Frequency Range

The operating frequency range of 300 MHz to 930 MHz can be covered without the use of an additional VCO
varactor diode. A frequency range extension down to 27 MHz can be realized by adding an external varactor
diode to the VCO tank.

Fig. 18: VCO tank circuit for extended frequency range

8.1 Board Component List (Fig. 18)

Part

Size

Value @

27 MHz

Value @

40 MHz

Value @

170 MHz

Tol.

Description

0805

VCO tank capacitor

VD1

SOD-323

varactor diode

CF1

0605

loop filter capacitor

CF2

0605

loop filter capacitor

CTX0

0603

TX coupling capacitor

CRX0

0603

RX coupling capacitor

0805

loop filter resistor

0805

loop filter resistor

0805

VCO tank inductor

LTX0

0805

TX impedance matching inductor

0603

LNA output tank inductor

CB1

0603

10%

blocking capacitor

CB2

0805

10%

blocking capacitor

CB6

0603

10%

blocking capacitor

Note: All other components are unchanged

RF1

CTX0

LTX0

CRX0

/
SD

CB1

CB2

RE/SCLK

IN_DTA

ASK/FSK

_LO

OUT_PA

IN_LNA

OUT_LNA

GAIN_LNA

IN_MIX

VD1

VCC

RF input

RF output

RPS

CF1

CF2

CB6

VCC_DIG

VEE_

I
G

VEE_LNA

TH7120

Antenna

matching

network

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 38 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

TX/RX Combining Network

9.1 Board Component List (Fig. 19)

Part

Size

Value @

315

MHz

Value @

433.92

MHz

Value @

868.3

MHz

Value @

915

MHz

CTX0 0603

10 pF

CTX1 0805

10 pF

NIP

CTX2 0805

18 pF

2.2 pF

3.9 pF

TBD

CTX3 0805

TBD

1.0 pF

TBD

CRX0 0603

100 pF

CRX1 0805

NIP

CRX2 0805

TBD

3.3 pF

TBD

LTX0

0805

150 nH

82 nH

TBD

LTX1

0805

TBD

33 nH

TBD

LRX1 0805

27 nH

18 nH

8.2 nH

TBD

LRX2 0805

TBD

10 nH

TBD

Note: NIP not in place, may be used optionally

Circuit Features

No TX/RX switch required

Direct connection to

/4 antenna possible

Fig. 19: Combining network schematic

9.2 LNA input impedances in receive mode

Mode

High gain

Low gain

Frequency

Re[S

]

Im[S

]

Re[S

]

Im[S

]

315 MHz

0.74

-0.32

450

0.86

-0.28

940

433 MHz

0.67

-0.41

390

0.81

-0.37

830

1.6 pF

868 MHz

0.35

-0.59

210

0.55

-0.63

470

915 MHz

0.32

-0.60

200

2.0 pF

0.52

-0.65

440

1.7 pF

IN_LNA

9.3 LNA input impedances in transmit mode

Mode

LNA off, Pin LNA is shorted

Frequency

Re[S

]

Im[S

]

315 MHz

-0.20

0.049

1.7 nH

433 MHz

-0.20

0.068

1.7 nH

868 / 915 MHz

-0.18

0.014

1.8 nH

IN_LNA

9.4 PA load impedances

Frequency

Re[S

]

Im[S

]

315 MHz

TBD

433 MHz

0.49

0.40

35 nH

868 MHz

-0.37

0.18

2 nH

915 MHz

TBD

OUT_PA

Note: This values represents the optimum load impedance seen by the output stage

LTX0

CTX0

CTX3

CRX1

CRX2

LRX1

LRX2

LTX1

CRX0

CTX1

CTX2

RF input

RF output

OUT_PA

IN_LNA

TH7120

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 40 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Reliability Information

Melexis devices are classified and qualified regarding suitability for infrared, vapor phase and wave soldering
with usual (63/37 SnPb-) solder (melting point at 183degC).
The following test methods are applied:

IPC/JEDEC J-STD-020A (issue April 1999)

Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface Mount Devices

CECC00802 (issue 1994)

Standard Method For The Specification of Surface Mounting Components (SMDs) of Assessed Quality

MIL 883 Method 2003 / JEDEC-STD-22 Test Method B102

Solderability

For all soldering technologies deviating from above mentioned standard conditions (regarding peak tem-
perature, temperature gradient, temperature profile etc) additional classification and qualification tests have to
be agreed upon with Melexis.

The application of Wave Soldering for SMD's is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.

For more information on manufacturability/solderability see quality page at our website:
http://www.melexis.com/

ESD Precautions

Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.

TH7120

27 to 930MHz

FSK/FM/ASK Transceiver

3901007120

Page 42 of 42

Data Sheet

Rev. 012

March/03

ELI

MIN

Disclaimer

Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the infor-
mation set forth herein or regarding the freedom of the described devices from patent infringement. Melexis
reserves the right to change specifications and prices at any time and without notice. Therefore, prior to de-
signing this product into a system, it is necessary to check with Melexis for current information. This product
is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or
life-sustaining equipment are specifically not recommended without additional processing by Melexis for each
application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential dam-
ages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data
herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis' rendering of
technical or other services.
© 2002 Melexis NV. All rights reserved.

For the latest version of this document. Go to our website at

www.melexis.com

Or for additional information contact Melexis Direct:

Europe and Japan:

All other locations:

Phone: +32 1367 0495

Phone: +1 603 223 2362

E-mail: sales_europe@melexis.com

E-mail: sales_usa@melexis.com

QS9000, VDA6.1 and ISO14001 Certified

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TH7120

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TH7120

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TH7120