PIN CONFIGURATION
32 PDIP
FEATURES
1M x 8 organization
Single +5V power supply
Fast access time : 100/120/150/200ns
Totally static operation
Completely TTL compatible
Operating current : 25mA
1
P/N:PM0137
REV. 4.3, JUL. 03, 2003
MX23C8000
8M-BIT [1M x 8] CMOS MASK ROM
Standby current : 15uA
Package
- 32 pin plastic DIP
- 32 pin plastic SOP
- 32 pin plastic PLCC
- 32 pin plastic TSOP
GENERAL DESCRIPTION
The MX23C8000 is a 5V only, 8M-bit, Read Only
Memory. It is organized as 1M words by 8 bits, oper-
ates from a single +5V supply, has a static standby mode,
and has an access time of 100/120/150/200ns. It is
designed to be compatible with all microprocessors and
similar applications in which high performance, large bit
storage and simple interfacing are important design con-
siderations.
MX23C8000 offers automatic power-down, with power-
down controlled by the chip enable (CE) input. When
CE goes high, the device automatically powers down
and remains in a low-power standby modes as long as
CE remains high.
32 SOP
32 PLCC
32 TSOP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
10
19
18
17
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
VCC
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
MX23C8000
A11
A9
A8
A13
A14
A17
A18
VCC
A19
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX23C8000
MX23C8000
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
1
4
5
9
13
14
17
20
21
25
29
32
30
A14
A13
A8
A9
A11
OE
A10
CE
Q7
A7
A6
A5
A4
A3
A2
A1
A0
DQ
Q1
Q2
VSS
Q3
Q4
Q5
Q6
A12
A15
A16
A19
VCC
A18
A17
MX23C8000
2
P/N:PM0137
REV. 4.3, JUL. 03, 2003
MX23C8000
PIN DESCRIPTION
Symbol
Pin Function
A0~A19
Address Inputs
Q0~Q7
Data Outputs
CE
Chip Enable Input
OE
Output Enable Input
VCC
Power Supply Pin (+5V)
VSS
Ground Pin
BLOCK DIAGRAM
CONTROL
LOGIC
OUTPUT
BUFFERS
Q0~Q7
CE
OE
A0~A19
ADDRESS
INPUTS
Y-DECODER
X-DECODER
Y-SELECT
8M BIT
ROM ARRAY
VCC
VSS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
0
C to 70
C
Storage Temperature
-65
C to 125
C
Applied Input Voltage
-0.5V to VCC+0.5
Applied Output Voltage
-0.5V to VCC+0.5
VCC to Ground Potential
-0.5V to 7.0V
Power Dissipation
1.0W
Note: minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -
2.0V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions,
input may overshoot VCC to VCC+2.0V for periods of up to 20ns.
3
P/N:PM0137
REV. 4.3, JUL. 03, 2003
MX23C8000
CAPACITANCE (Ta = 25
C, f=1.0MHz (Note 2))
Item
Symbol
MIN.
MAX.
UNIT
Conditions
Input Capacitance
CIN
-
10
pF
VIN=0V
Output Capacitance
COUT
-
10
pF
VOUT=0V
DC CHARACTERISTICS (Ta = 0
C ~ 70
C, VCC = 5.0V
10%)
Item
Symbol
MIN.
MAX.
Conditions
Output High Voltage
VOH
2.4V
-
IOH = -1.0mA
Output Low Voltage
VOL
-
0.4V
IOL = 2.1mA
Input High Voltage
VIH
2.2V
VCC+0.3V
Input Low Voltage
VIL
-0.3V
0.8V
Input Leakage Current
ILI
-
10uA
VIN=0 to 5.5V
Output Leakage Current
ILO
-
10uA
VOUT=0 to 5.5V
Power-Down Supply Current
ICC3
-
15uA
CE>VCC-0.2V
Standby Supply Current
ICC2
-
1.0mA
CE=VIH
Operating Supply Current
ICC1
-
25mA
Note 1
Note:
1. Measured with device selected at f=5MHz and output unloaded.
2. This parameter is periodically sampled and is not 100% teseted.
3. Output low-impedance delay (tLA) is measured from CE going low.
4. Output high-impedance delay (tHZ) is measured from CE going high.
AC CHARACTERISTICS (Ta = -10
C ~ 70
C, VCC = 5.0V
10%)
23C8000-10
23C8000-12
23C8000-15
23C8000-20
PARAMETER
SYMBOL MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
CONDITIONS
Cycle Time
tCYC
100ns -
120ns
-
150ns
-
200ns
-
Address Access Time
tAA
-
100ns
-
120ns
-
150ns
-
200ns
Output Hold Time After
tOH
0ns
-
0ns
-
0ns
-
0ns
-
Address Change
Chip Enable Access Time
tCE
-
100ns
-
120ns
-
150ns
-
200ns
Output Enable/Chip Select tOE
-
50ns
-
50ns
-
50ns
-
50ns
Access Time
Output Low Z Delay
tLZ
0ns
-
0ns
-
0ns
-
0ns
-
Note 3
Output High Z Delay
tHZ
-
20ns
-
20ns
-
20ns
-
20ns
Note 4
4
P/N:PM0137
REV. 4.3, JUL. 03, 2003
MX23C8000
AC Test Conditions
Input Pulse Levels
0.4V~2.4V
Input Rise and Fall Times
10ns
Input Timing Level
1.5V
Output Timing Level
0.8V and 2.0V
Output Load
See Figure
TIMING DIAGRAM
PROPAGATION DELAY FROM ADDRESS (CE/OE=ACTIVE)
VALID DATA
VALID ADDRESS
ADDRESS
INPUTS
tCYC
tAA
DATA OUT
tOH
Note:
No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
DOUT
C<100pF
IOL (load)=2.1mA
IOH (load)=-1mA
PROPAGATION DELAY FROM CHIP ENABLE (ADDRESS VALID)
tHZ
tCE
tOE
tLZ
OE
DATA OUT
CE
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