DA1017.002
29 May, 2002
1(6)
MAS1017
AM Receiver IC
High Sensitivity
Very Low Power Consumption
Wide Supply Voltage Range
Power Down and Power Up Control
High Selectivity by Crystal Filter
DESCRIPTION
The MAS1017 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to
receive time signals in the frequency range from 40
kHz to 100 kHz. There are only a few external
components needed. The circuit has a preamplifier,
wide range automatic gain control, demodulator and
output comparator built in. The output signal can be
processed directly with an additional digital circuitry to
extract the data from the received signal.
FEATURES
APPLICATIONS
Highly Sensitive AM Receiver
Wide Supply Voltage Range
Very Low Power Consumption
Power Down and Power Up Control
Only a Few External Components Needed
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
Time Signal Receiver for DCF77 (Germany)
BLOCK DIAGRAM
AGC Amplifier
Demodulator
&
Comparator
Power Supply/Biasing
RFI
DCF
PUP
QI
QO
PDN
VDD
VSS
AGC
DEC
DA1017.002
29 May, 2002
2(6)
PAD LAYOUT
DIE size = 2.09 x 1.59 mm; PAD size = 100 x 100
m
Substrate is connected to VDD. Please make sure that VDD is bonded first.
Note: Coordinates are calculated using VDD as a centre point.
Pad Identification
Name
X-coordinate
Y-coordinate
Note
Power Supply Voltage
VDD
0
m
0
m
Demodulator Capacitor
DEC
244
m
8
m
AGC Capacitor
AGC
520
m
8
m
Power Up Input
PUP
759
m
8
m
1
DCF Signal Output
DCF
1075
m
8
m
2
Quarz Filter Input
QI
1038
m
1625
m
Quarz Filter Output
QO
760
m
1625
m
Power Down Input
PDN
483
m
1625
m
3
Receiver Input
RFI
243
m
1625
m
Power Supply Ground
VSS
-15
m
1605
m
Notes:
1) See power down control table below.
-
Internal pull-down resistor > 1 M
to VSS
2) DCF = VSS when carrier amplitude at maximum; DCF = VDD when carrier amplitude is reduced (25%
modulated)
-
the output is a current source/sink with |I
OUT
| > 5
A
-
at power down the output is high impedance
3) See power down control logic table below.
- Internal pull-up resistor > 1M
to VDD
PDN
PUP
Power Down
VSS
VSS
NO
VSS
VDD
NO
VDD
VSS
YES (In power down if both PDN and PUP are left unconnected)
VDD
VDD
NO
VDD DEC
QI
AGC
DCF
VSS RFI
PDN QO
1588 m
2094 m
MAS1017
PUP
DA1017.002
29 May, 2002
3(6)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Min
Max
Unit
Supply Voltage
V
DD
-V
SS
-0.3
5.0
V
Input Voltage
V
IN
V
SS
-0.3
V
DD
+0.3
V
Power Dissipation
P
MAX
100
mW
Operating Temperature
T
OP
-20
70
o
C
Storage Temperature
T
ST
-40
120
o
C
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.4V, Temperature = 25C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating Voltage
V
DD
1.10
3.60
V
Current Consumption
I
DD
40
100
A
Stand-By Current
I
DDoff
0.1
A
Input Range
f
IN
40
100
kHz
Sensitivity
V
IN
0.001
20
mVrms
Input Levels |l
IN
|<0.5
A
V
IL
V
IH
V
DD
0.3
0.3
V
Output Current
V
OL
<0.2 V
DD
;V
OH
>0.8 V
DD
|I
OUT
|
5
A
Output Pulse
T
0
50
140
ms
T
1
150
230
ms
Startup Time
T
Start
8
s
Output Delay Time
T
Delay
50
ms
DA1017.002
29 May, 2002
4(6)
TYPICAL APPLICATION
Note 1: Ferrite Antenna and Crystal
The crystal as well as ferrite antenna frequencies are chosen according to the time signal system frequency.
DCF-77 transmitter frequency is 77.5 kHz. The ferrite antenna center frequency has to be tuned to 77.5 kHz.
The optimal crystal frequency is 77503 Hz but also 77500 Hz crystal can be used. The shunt capacitance of the
crystal should be as close as possible to internal shunt capacitance compensation capacitor of 0.75 pF for
optimal noise filtering.
Note 2: AGC and DEC Capacitors
The AGC and DEC capacitors should have low leakage currents due to very small 40 nA signal currents through
the capacitors. The insulation resistance of these capacitors should be higher than 70 M
. Also probes with at
least 100 M
impedance should be used for voltage probing of AGC and DEC pins.
AG C Am plifier
Dem odulator
&
Com parator
P ow er S upply/Biasing
RFI
DCF
Q I
Q O
V D D
AG C
DE C
V SS
Receiver
output
Ferrite-
An tenna
77503 Hz
+1.1V to +3.6V
P U P
470 nF
47 nF
P D N
DA1017.002
29 May, 2002
5(6)
SAMPLES IN SBDIL 20 PACKAGE
NC 1
VDD 2
NC 3
DEC 4
AGC 5
NC 6
PUP 7
DCF 8
NC 9
NC 10
20 VSS
19 NC
18 RFI
17 PDN
16 NC
15 QO
14 NC
13 QI
12 NC
11 NC
PIN DESCRIPTION
Pin Name
Pin
Type
Function
Note
NC
1
VDD
2
P
Positive power supply
NC
3
DEC
4
AO
Demodulator capacitor
AGC
5
AO
AGC capacitor
NC
6
PUP
7
AI
Power up input
1
DCF
8
DO
Demodulator output
2
NC
9
NC
10
NC
11
NC
12
QI
13
AI
Quartz filter input
NC
14
3
QO
15
AO
Quartz filter output
NC
16
PDN
17
AI
Power down input
4
RFI
18
AI
Receiver input
NC
19
VSS
20
G
Power supply ground
Notes:
1) See power down control table on page 2.
-
Internal pull-down resistor > 1 M
to VSS
2) DCF = VSS when carrier amplitude at maximum; DCF = VDD when carrier amplitude is reduced (25%
modulated)
-
the output is a current source/sink with |I
OUT
| > 5
A
-
at power down the output is high impedance
3) Pin 14 between quartz crystal filter pins must be connected to VSS to eliminate package leadframe parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
4) See power down control logic table on page 2.
- Internal pull-up resistor > 1M
to VDD
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