GT-48002A
Switched Fast Ethernet Controller
for 100BaseX
Preliminary Rev.
Revision 1.2
8/19/97
Please contact Galileo Technology for possible
updates before finalizing a design.
FEATURES
www.galileoT.com support@galileoT.com Tel: +1-408.451.1400 Fax: +1-408.451.1404
Single-chip, low cost, Switched Fast Ethernet
Controller
- Provides packet switching functions between two
10/100Mbps, auto-negotiated on-chip Fast
Ethernet ports and the PCI expansion port
- Switch expansion via 1Gbps PCI bus
- Ideal uplink/server connect for the 10 Mbps GT-
48001A Switched Ethernet Controller
GalNet Architecture Family Member
- Connects seamlessly to other GalNet Family
Devices including GT-48001A 10BaseX and GT-
48003 100VG-AnyLAN controllers
Incorporates two 802.3 compliant 10/100Mbps Media
Access Controllers
- Direct Interface to MII (Media Independent
Interface)
- Half/Full Duplex Support (up to 200 Mbps/port)
- IEEE 802.3 100Base-TX, T4, and FX compatible
Full MII Management Support (MDC/MDIO) via CPU
Auto-negotiation supported through MII Interface
CRC generation for CPU generated packets
High-Performance Distributed Switching Engine
- Performs forwarding and filtering at full wire speed
- 148,800 packets/s on each Ethernet port
- Flexible software or hardware intervention in
packet routing decisions
Direct support for packet buffering
- Glueless interface to 1or 2Mbyte of 60ns EDO
DRAM
- Up to 1K buffers, 1536-bytes each, dynamically
allocated to the receive and PCI ports
Supports `Store and Forward' switching approach
- Low last-bit in to first-bit out delay
- Allows bridging between higher/lower speed
interfaces (FDDI, ATM, WAN)
High observability LED interface
- 6 parallel LED outputs per port, including internal
"monostable" function to enable viewing of
dynamic signals
- 3 pin serial LED interface for additional status
information per port
Advanced address recognition
- Intelligent address recognition mechanism enables
forwarding rate at full wire speed
- Self-learning mechanism
- Supports up to 8K Unicast addresses and
unlimited Multicast/Broadcast addresses
- Broadcast storm filtering
PCI Rev 2.1 interface for switch expansion and
management CPU connection
- Up to 3 GT-48002A devices per PCI bus segment
without PCI-to-PCI bridging
- Up to 32 GalNet devices in a single switch
- Standard CPU connection for management
- Simple interface to other networking interfaces
(ATM, FDDI, etc.)
Extensive network management support
- Repeater MIB and PCI counters
- Address aging support
- Hardware assist for Spanning Tree algorithm
- RMON Station-to-Station connectivity matrix
- CPU access to Address Table
- Ability to define static addresses
- Monitoring (sniffer) mode
HP-EASE Packet sampling management technology
- Takes "snapshots" of packets at programmable
intervals
- Allows for the implementation of HP-EASE or
sampled RMON with low-cost CPUs
208 pin PQFP package
DMA
Transmit
Receive
Collision
Forwarding Unknown
Sniffer
Half/Full Duplex
Status
Switching
Engine
PCI Bus
Data
Address
Control
Self-Learning &
Address
Recognition
Engine
DRAM
Controller
Frame
Controller
G
AL
N
ET
Controller
RMON FIFO
Control
Control
PCI Counters
2 x MIB Counters
PCI
Address Table
Statistics Counters
Configuration Registers
Intervention
Mode
Control
Packet Buffers
Serial
Switching
G
AL
N
ET
Sniffer
Control
Miscellaneous
2x
LED
Control
DMA
PCI Bus Controller
1 0 / 1 0 0 M b p s
MII
Interface
Port 0
Rx
FIFO
Tx
FIFO
1 0 / 1 0 0 M b p s
MII
Interface
Port 1
Rx
FIFO
Tx
FIFO
Receive Buffer Full
GT-48002A Switched Fast Ethernet Controller
2
Revision 1.2
Contents
1. Functional Overview ........................................................................................................... 6
1.1
The GalNet Switching Architecture .......................................................................................................... 6
1.2
Fast Ethernet Ports .................................................................................................................................. 6
1.3
Address Recognition ................................................................................................................................ 7
1.4
CPU Packet Routing ................................................................................................................................ 7
1.5
Intervention Mode ..................................................................................................................................... 7
1.6
Network Management Features ............................................................................................................... 7
1.7
DRAM Interface ........................................................................................................................................ 7
1.8
PCI Interface ............................................................................................................................................ 8
2. Pin Information .................................................................................................................... 9
2.1
Logic Symbol ............................................................................................................................................ 9
2.2
Pin Functions and Assignment .............................................................................................................. 10
3. Operational Overview ....................................................................................................... 15
3.1
Enabling/Disabling the GT-48002A ........................................................................................................ 15
3.2
Basic Operation ...................................................................................................................................... 15
3.3
Address Learning ................................................................................................................................... 16
3.4
Packet Buffering ..................................................................................................................................... 16
3.5
Packet Forwarding ................................................................................................................................. 16
3.6
The GalNet Protocol ............................................................................................................................... 16
3.7
Terminology ............................................................................................................................................ 16
4. MAC Address Learning Process...................................................................................... 18
4.1
Address Recognition .............................................................................................................................. 18
4.2
Recovery Process .................................................................................................................................. 18
4.3
Address Aging ........................................................................................................................................ 19
4.4
Static Addresses .................................................................................................................................... 19
4.5
Address Recognition Failure .................................................................................................................. 19
5. GT-48002A Buffers and Queues ...................................................................................... 20
5.1
Rx Buffer Threshold Programming ......................................................................................................... 21
6. Packet Forwarding ............................................................................................................ 22
6.1
Forwarding a Unicast Packet to a Local Port ......................................................................................... 22
6.2
Forwarding a Unicast Packet to a Port in a Different GalNet Device ..................................................... 22
6.3
Forwarding a Multicast Packet ............................................................................................................... 23
6.3.1
Local Ports .............................................................................................................................. 23
6.3.2
Between GalNet Devices ........................................................................................................ 23
6.3.2.1
CPU Disabled ......................................................................................................... 23
6.3.2.2
CPU Enabled .......................................................................................................... 23
6.4
Forwarding a Packet to the CPU Directly ............................................................................................... 24
6.5
Forwarding a Packet from the CPU to a GalNet Device ........................................................................ 26
6.6
CRC Generation ..................................................................................................................................... 27
6.7
Tx Watchdog Timer ................................................................................................................................ 27
7. Device Table Operation .................................................................................................... 28
7.1
Automatic Device Table Initialization ...................................................................................................... 28
7.2
Manual Device Table Initialization .......................................................................................................... 28
7.3
Programming Device Numbers .............................................................................................................. 28
Switched Fast Ethernet Controller
Revision 1.2
3
8. Unicast Intervention Mode ................................................................................................ 29
8.1
Unicast Intervention Mode Address Space ............................................................................................ 30
9. Address Table .................................................................................................................... 31
10. GalNet Messaging Protocol .............................................................................................. 33
10.1 GalNet Protocol Region ......................................................................................................................... 33
10.2 GalNet Messages Between Devices ..................................................................................................... 35
10.2.1 NEW_ADDRESS Message between GalNet devices ............................................................ 35
10.2.2 BUFFER_REQUEST Message between GalNet devices ...................................................... 36
10.2.3 START_OF_PACKET Message between GalNet devices ..................................................... 36
10.2.4 PACKET_TRANSFER Message between GalNet devices .................................................... 37
10.2.5 END_OF_PACKET Message between GalNet devices ......................................................... 37
10.3 GalNet Messages Between a GalNet Device and a CPU ...................................................................... 38
10.3.1 NEW_ADDRESS Message (GalNet to CPU) ......................................................................... 38
10.3.2 NEW_ADDRESS Message (CPU to GalNet) ......................................................................... 39
10.3.3 BUFFER_REQUEST Message (GalNet to CPU) ................................................................... 40
10.3.4 BUFFER_REQUEST Message (CPU to GalNet) ................................................................... 40
10.3.5 START_OF_PACKET Message (GalNet to CPU).................................................................. 41
10.3.6 START_OF_PACKET Message (CPU to GalNet).................................................................. 41
10.3.7 PACKET_TRANSFER Message (GalNet to CPU 16 Block Buffer)........................................ 42
10.3.8 PACKET_TRANSFER Message (GalNet to CPU in Unicast Intervention Mode)................... 42
10.3.9 PACKET_TRANSFER Message (CPU to GalNet) ................................................................. 43
10.3.10 END_OF_PACKET Message (GalNet to CPU 16 Block Buffer)............................................. 44
10.3.11 END_OF_PACKET Message (GalNet to CPU in Unicast Intervention Mode) ....................... 44
10.3.12 END_OF_PACKET Message (CPU to GalNet) ...................................................................... 45
11. PCI Bus Operation ............................................................................................................. 46
11.1 PCI Configuration Header Registers ..................................................................................................... 46
11.2 Accessing DRAM and Internal Registers through the PCI Interface ...................................................... 46
11.3 PCI Bandwidth/Performance Issues ...................................................................................................... 46
11.4 Plug-and-Play Considerations In PCI Systems ...................................................................................... 47
11.5 Unused PCI Bus in Stand-Alone Systems ............................................................................................. 47
11.6 PCI Bus Arbiter in Multiple GalNet Device Systems .............................................................................. 47
12. Fast Ethernet Interfaces ....................................................................................................48
12.1 10/100 MII Compatible Interface ............................................................................................................ 48
12.2 Media Access Control (MAC) ................................................................................................................ 48
12.3 Auto-negotiation ..................................................................................................................................... 48
12.3.1 Disabled.................................................................................................................................. 48
12.3.2 Enabled .................................................................................................................................. 48
12.3.3 Auto-negotiation Control Per Port........................................................................................... 49
12.3.4 Auto-Negotiation, Software Detection .................................................................................... 50
12.4 Backoff Algorithm Options ..................................................................................................................... 50
12.5 Data Blinder ........................................................................................................................................... 50
12.6 Inter-Packet Gap (IPG) .......................................................................................................................... 50
12.7 10/100 Mbps MII Transmission .............................................................................................................. 50
12.8 10/100 Mbps MII Reception ................................................................................................................... 51
12.9 10/100 Mbps Full-Duplex Operation ...................................................................................................... 52
12.10 Illegal Frames ........................................................................................................................................ 52
12.11 Partition Mode ........................................................................................................................................ 52
12.11.1 Enabling Partition Mode ......................................................................................................... 52
12.11.2 Entering Partition State........................................................................................................... 52
12.11.3 Exiting from Partition State ..................................................................................................... 52
GT-48002A Switched Fast Ethernet Controller
4
Revision 1.2
12.12 Back-pressure ........................................................................................................................................ 52
12.13 VLAN Tagging Support .......................................................................................................................... 53
13. MII Management Interface (SMI)....................................................................................... 54
13.1 SMI Cycles ............................................................................................................................................ 54
13.1.1 SMI Timing Requirements....................................................................................................... 54
13.2 Link Detection and Link Detection Bypass (ForceLinkPass*) ............................................................... 56
14. Network Management Support ........................................................................................ 57
14.1 Repeater MIB and PCI Counters ........................................................................................................... 57
14.2 Station-to-Station Connectivity Matrix .................................................................................................... 57
14.2.1 Data Structure Format............................................................................................................. 58
14.3 Monitoring (Sniffer) Mode ....................................................................................................................... 59
14.4 Spanning Tree Support .......................................................................................................................... 59
14.5 Broadcast Storm Filtering ....................................................................................................................... 59
15. HP-EASE Packet Sampling Technology ......................................................................... 60
15.1 HP EASE Technology Overview ............................................................................................................ 60
15.2 EASE Functionality on the GT-48002A .................................................................................................. 61
15.3 Ease_Register ........................................................................................................................................ 61
15.4 EASE Interrupts ...................................................................................................................................... 61
15.5 Sampled Packet Indication ..................................................................................................................... 62
15.6 Error Source Indications ......................................................................................................................... 63
15.7 Enabling/Disabling EASE Functionality .................................................................................................. 64
15.8 Interaction With Other GT-48002A Features .......................................................................................... 64
16. DRAM Interface and Usage .............................................................................................. 65
17. LED Support ...................................................................................................................... 65
17.1 Led Indications Interface Description ..................................................................................................... 65
17.2 Detailed LED Signal Description ............................................................................................................ 65
17.2.1 Primary Port Status LED ......................................................................................................... 65
17.2.1.1 Primary Port Status LED in Mode 0: (LEDMode input is LOW) ............................. 66
17.2.1.2 Status LED blink timing (Mode 0) ........................................................................... 66
17.2.1.3 Primary Port Status LED (Mode 1): (LEDMode input is HIGH).............................. 66
17.2.2 Transmit data in progress ....................................................................................................... 67
17.2.3 Receive data in progress ........................................................................................................ 67
17.2.4 Collision active ........................................................................................................................ 67
17.2.5 Full/Half duplex ....................................................................................................................... 67
17.2.6 Receive Buffer Full.................................................................................................................. 67
17.2.7 Forwarding of unknown packets enabled................................................................................ 67
17.2.8 The port is configured as Sniffer ............................................................................................. 67
17.2.9 Link Fail State ......................................................................................................................... 67
17.2.10 Partition State.......................................................................................................................... 68
17.2.11 Secondary Port Status LED .................................................................................................... 68
17.2.12 Pure Port Status LED.............................................................................................................. 68
17.3 LED Signals Timing Type ....................................................................................................................... 68
17.3.1 Static LED Signals .................................................................................................................. 68
17.3.2 Dynamic Internal Signals: ....................................................................................................... 68
17.4 Serial LED Interface Description ............................................................................................................ 68
17.4.1 Table of Internal Activities/Status Driven via the Serial LED Interface.................................. 69
17.5 Parallel LED Interface Description ......................................................................................................... 70
Switched Fast Ethernet Controller
Revision 1.2
5
18. Interrupts ............................................................................................................................ 71
19. RESET Configuration ........................................................................................................ 71
19.1 Configuration Pins ................................................................................................................................. 71
19.2 Configuration Input Timings ................................................................................................................... 71
20. Switch Expansion .............................................................................................................. 72
21. Development Tools............................................................................................................ 73
21.1 Evaluation Platforms .............................................................................................................................. 73
21.2 Verilog Models ....................................................................................................................................... 73
21.3 Reference Designs ................................................................................................................................ 73
21.4 Complimentary Products ....................................................................................................................... 73
22. Register Tables .................................................................................................................. 74
22.1 Register Map ......................................................................................................................................... 74
22.2 Internal Control Registers ...................................................................................................................... 75
22.3 Port MIB Counters (2 Blocks), Offset: 0x040000 - 0x0400ac ................................................................ 84
22.4 PCI Global Counters, Offset: 0x140040 - 0x140044 ............................................................................. 88
22.5 SMI Register, Offset: 0x14004c ............................................................................................................. 88
22.6 PCI Configuration Registers .................................................................................................................. 88
23. Pinout for 208 pin PQFP (sorted by number) ................................................................. 92
23.1 Package/Pin Drawing ............................................................................................................................ 94
24. DC Characteristics - PRELIMINARY/SUBJECT TO CHANGE ........................................ 95
24.1 Absolute Maximum Ratings ................................................................................................................... 95
24.2 Recommended Operating Conditions .................................................................................................... 95
24.3 DC Electrical Characteristics Over Operating Range ............................................................................ 95
24.4 Thermal Data ......................................................................................................................................... 96
25. AC Timing - PRELIMINARY/SUBJECT TO CHANGE....................................................... 97
26. Functional Waveforms ...................................................................................................... 99
26.1 PCI Read/Write Cycle .......................................................................................................................... 100
27. Packaging ......................................................................................................................... 101
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