Features
Smallest RISC CPU core (1.1 sq. mm)
Best-of-class power rating (.5mW/MHz)
MIPS-I and MIPS-II compatible
Code compression using MIPS16
85MHz at 2.5 V in 0.25 micron process
Intermixing of 16- and 32-bit code
1.8 V in .18 micron process- available
soon
Overview
The 4102
TM
TinyRISC MIPS processor core extends LSI Logic's embedded RISC
processor family. This core is the second generation of the widely used
TinyRISC
TM
MIPS processor implementation using the MIPS16, Application
Specific Extension (ASE). The core can execute both 16-bit and 32-bit
instructions intermixed in the same program allowing for improved memory
utilization. The MIPS16 ASE enables the development of compact code required
for embedded applications.
The 4102 TinyRISC
TM
offers the smallest CPU core size and lowest power rating
in its class developed in 0.25-micron (.18 Leff) technology, 2.5V process. As
such power dissipation is .5mW/MHz.
LSI introduces the EasyMACRO concept (EZ4102) for integrating the 4102
TinyRISC
TM
CPU core with the most commonly used system building blocks to
reduce development time. This is accomplished by combining and integrating
the blocks into a hard macro function that is treated as a single core.
The EZ4102 building blocks include a memory management unit,
multiply/divide unit, a bus interface controller and cache controller, UART,
EJTAG, and two 32 bit timers. In addition to these attributes, the
EasyMACRO was designed for System-On-a-Chip integration through LSI
Logic's CoreWare design methodology. Integration with other CoreWare
library elements provides the flexibility to develop a variety of solutions from a
custom CPU to a full System-On-a-Chip solution.
TinyRISC
TM
4102 MIPS Processor Core
Benefits
System cost savings
Well suited for portable application
solutions
Easy migration to TinyRISC
TM
Compact code allows memory size
efficiences
Low power consumption
Optimized performance vs. code size
Core size reduction and increased
operating frequency
The 4102 TinyRISC
TM
MIPS processor core, the smallest MIPS core, 1.1 sq. mm, shrinks system cost and
reduces time to market.
LSI Logic logo design, CoreWare and CoreWare logo design
and G10 are registered trademarks of LSI Logic Corporation.
All other brand and product names may be trademarks of
their respective companies.
LSI Logic Corporation reserves the right to make changes to
any products and services herein at any time without notice.
LSI Logic does not assume any responsibility or liability aris-
ing out of the application or use of any product or service
described herein, except as expressly agreed to in writing by
LSI Logic; nor does the purchase, lease, or use of a product or
service from LSI Logic convey a license under any patent
rights, copyrights, trademark rights, or any other of the intel-
lectual property rights of LSI Logic or of third parties.
Copyright 1999 by LSI Logic Corporation.
All rights reserved.
For more information please call:
Europe +32.11.300.351
www.lsilogic.com
LSI Logic Corporation
North American Headquarters
Milpitas, CA
Tel: 800.574.4286
LSI Logic Europe Ltd
European Headquarters
United Kingdom
Tel: 44.1344.426544
Fax: 44.1344.481039
LSI Logic KK Headquarters
Tokyo, Japan
Tel: 81.3.5463.7821
Fax: 81.3.5463.7820
Order No. C20027.A
999.1K.CM.XXX Printed in USA
ISO 9000 Certified
TinyRISC
TM
4102 MIPS Processor Core
C Bus
Extended Debug MACRO
Easy Macro (EZ 4102)
TR4102
CPU
and
FAST
MDU
MMU
BIU and Cache
Controller
(BBCC)
Timers
EJTAG
UART
Flexlink
Serial ICE
EJTAG Interface
PC Trace Output
B Bus
F Bus
FBus
Controller
Clock
Controller
TLB RAM
Caches and Tags
Easy Macro in a Typical System
Support Products
A complete environment for hardware development and software debugging is
provided by connecting a PC or SUN Workstation to LSI's 4102 evaluation
board, BDMR4102. A CD-ROM containing executable programs along with
source code, RTOS (Real-Time Operating System) BSP (Board Support
Package), and documentation is included with the BDMR4102
The TinyRISC
TM
EZ4102 is supported with comprehensive tools for embedded
system development. Design tools include a Verilog/VHDL compatible RTL
model, a system verification environment (SVE), complete netlist including tim-
ing, and example script files to assist EZ4102 integration.
CoreWare
CoreWare design facilitates System-On-a-Chip design integration, delivering
unmatched market advantages. This methodology is proven and complete offer-
ing the technology and application know-how to put an entire system on a single
chip. Industry-standard functions or cores, are combined with on-chip memory
and user-defined logic to create designs efficiently and rapidly.
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