4-Port 84C30A
4-1
MD400151/C
1
96339
84C30A
4-Port
Ethernet Controller
Features
s
Low Power CMOS Technology
s
4-Port Ethernet Controller Optimized for
Switching Hub, Multiport Bridge/Router,
Server Applications
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Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards
for Thicknet (10Base-5), Thin Net (10Base-2)
and Twisted Pair (10Base-T)
s
Standard 10MBit/sec Serial Ethernet
s
Selectable Little Endian/Big Endian Transmit Byte
Ordering for FIFO Interface for Intel/Motorola
Compatibility
s
Open Bus Interface
s
Programmability of Double Word Threshold
Count for Space Available/Data Available Ready
Condition for Transmit/Receive FIFO's
s
Auto Retransmit Upon Collision Sense
s
Preamble Generation and Removal
s
Automatic 32-Bit FCS (CRC) Generation and
Checking
s
Collision Handling, Transmission Deferral and
Retransmission with Automatic Jam and
Backoff Functions
s
Error Interrupt and Status Generation
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Single 5 V
5% Power Supply
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Standard CPU and Peripheral Interface
Control Signals
s
Independent 128 Byte Transmit/Receive FIFOs
on each Port
- 1 G Bits/sec (133 M Bytes/sec) Peak Data Rate
in 32 Bit Mode.
s
Loopback Capability for Diagnostics
s
32 Bit FIFO Data Path
s
Inputs and Outputs TTL Compatible
s
The Following Additional Features can be
Programmed for the 84C30A
- 64 bit Multicast Filter
- Reports Status of "SQE" During Transmits
- Transmit No CRC Mode
- Transmit No Preamble Mode
- Transmit Packet Autopadding Mode
- Receive CRC Mode
- Disable Self-Receive on Transmits Mode
- Disable Further Transmissions when Both
Transmit Status Registers are Full
- Disable Loading the Transmit Status for
Successfully Transmitted Packets
- Disable the Receive Interrupts Independent
of the Receive Command Register Setting
s
Transmit Status on a Per Packet Basis Reports the
Following
- Occurrence of a Transmit FIFO Underflow
- Transmit Collision Occurrence
- 16 Collision Occurrence
- Carrier Sense Error During Transmission
- 10 Mbit/sec Transmit Clock Detect
- Late Collision Occurrence
- Transmission Successful
- Transmission Deferred
s
Each Port Includes the Following Counters or
Status Bits for Network Management Statistics
- 16 Bit Short Receive Frame Counter
- 16 Bit Alignment Error Counter
- 16 Bit CRC Error Counter
- 8 Bit Oversize Receive Frame Counter
- 16 Bit Transmit Collision Counter
- 16 Bit Total Collision Counter
- Transmit Status Bits for "Carrier" and
"SQE" During Transmits
s
Full Duplex Operation
- Provides 20 Mbps Bandwidth for Switched
Networks
- Supports AutoDUPLEX Mode for Automatic
Full Duplex Operation
s
208 Pin PQFP package
Full Duplex
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
4-Port 84C30A
4-2
2
MD400151/C
Table of Contents
1.0 Pin Description
2.0 Introduction
3.0 Functional Description
3.1 Frame Format
3.2 Packet Transmission per Port
3.2.1 Controlling Transmit Packet
Encapsulation
3.2.2 Transmission Initiation/Deferral
3.2.3 Collision on Transmit
3.2.4 Transmit Termination Conditions
3.2.5 Conditions That Will Cause a Port
TXRET Pin to go HIGH
3.2.6 Detecting and Clearing of a
Transmit Retry Condition
3.3. Packet Reception Per Port
3.3.1 Preamble Processing
3.3.2 Address Matching
3.3.3 Terminating Reception
3.3.4 Using the Rxabort Pins to Terminate
Reception of a Packet
3.3.5 Receive Discard Conditions
3.4 System Interface
3.5 FIFO Interface
3.5.1 Little and Big Endian Format
3.5.2 Transmit FIFO Interface
3.5.3 Receive FIFO Interface
3.5.4 Special Conditions on
RXRD_TXWR Clock Input
3.6 Register Interface
3.6.1 Internal Channel Register Addressing
Table
3.6.2 Station Address Register
3.6.3 Transmit Command Register
3.6.4 Transmit Status Register
3.6.5 Receive Command Register
3.6.6 Receive Status Register
3.6.7 Configuration Registers
3.6.8 FIFO Threshold Register
3.6.8.1 FIFO Threshold Register
Address Settings Table
3.6.9 Defer Register Calculations for the
84C30A
3.6.10 Transmit Control/Product I.D.
Register
3.7 Counters
4.0 DC Characteristics
5.0 AC Characteristics
5.01 Command/Status Interface Read Timing
5.02 Command/Status Interface Write Timing
6.0 Ethernet Transmit and Receive
Interface Timing
6.01 Ethernet Transmit Interface Timing
6.02 Ethernet Receive Interface Timing
7.0 Transmit Data Interface Timing
7.01 Transmit Data Interface Write Timing 1
7.02 Transmit Data Interface Write Timing 2
8.0 Receive Data Interface Timing
8.01 Receive Data Interface Read Timing 1
8.02 Receive Data Interface Read Timing 2
9.0 Transmit Data Interface Timing on
Exception Conditions
10.0 Receive Data Interface Timing on
Exception Conditions
Illustrations
Figure 1. Functional Block Diagram of the 84C30A
Figure 2. 84C30A Pin Configuration
Figure 3. Typical Application Example
4-Port 84C30A
4-3
MD400151/C
3
Pin
Pin Name
I/O
Description
Chip Registers' Interface
22
ENREGIO
I
This active low input enables the chip for register operations. This input must be
low before any port's registers can be written or read.
4
W R
I
For a selected port within the chip, this input acts as a write strobe for one of the port's
registers. The port is selected through the REGPS[1:0] inputs and the register is
addressed through the A[2:0] address inputs. The data being written appears on the
CDST[7:0] data lines and must be set up relative to the rising edge of the write strobe.
This input is active low.
5
RD
I
For a selected port within the chip, this input acts as a read strobe for one of the port's
registers. The port is selected through the REGPS[1:0] inputs and the register is
addressed through the A[2:0] address inputs. When the read strobe is active low,
the output drivers for CDST[7:0] data bus are enabled. Valid register data appears
on the data bus a specified time before the rising edge of the read strobe.
21, 20
REGPS[1:0]
I
These inputs are used to select which port's registers are read or written by asserting
the RD or WR read or write strobe inputs. Binary values of 00 through 11 select
channels 1 through 4 respectively with REGPS1 being the MSB of the binary value.
153,
A[3:0]
I
These inputs are the address lines used to select which register within a port is being
6, 7, 8
read or written. A3 has an internal pull down.
5-8
CDST[7:0]
I/O
These bidirectional lines carry register data to or from the internal registers of each
9-12
port in the chip. These lines are nominally high impedance until their output drivers
are enabled by the RD and ENREGIO input pins being driven low.
7
INT_1
O
This output is driven high by a variety of port #1 transmit and receive interrupt
conditions. It remains high until the port #1 status register containing the reason for
the interrupt is read.
61
INT_2
O
This output is driven high by a variety of port #2 transmit and receive interrupt
conditions. It remains high until the port #2 status register containing the reason for
the interrupt is read.
68
INT_3
O
This output is driven high by a variety of port #3 transmit and receive interrupt
conditions. It remains high until the port #3 status register containing the reason for
the interrupt is read.
77
INT_4
O
This output is driven high by a variety of port #4 transmit and receive interrupt
conditions. It remains high until the port #4 status register containing the reason for
the interrupt is read.
49
RESET
I
This input is an active low chip reset. During reset all registers are reset to zero, all
FIFO's are cleared, all counters are reset to zero, and all the inputs to the output
drivers for the RXDC and TXRET outputs are driven high.
Receive and Transmit FIFO Interface
31
RXINTEN
I
This is an active low input that acts as a chip enable to enable the receiver interface.
Driving this pin active enables the output drivers for the RXDC_1, RXDC_2,
RXDC_3, RXDC_4, RXRDY_1, RXRDY_2, RXRDY_3, and RXRDY_4 pins. Also,
this pin must be driven active before receive FIFO reads can be performed.
32
TXINTEN
I
This is an active low input that acts as a chip enable to enable the transmitter
interface. Driving this pin active enables the output drivers for the TXRET_1,
TXRET_2, TXRET_3, TXRET_4, TXRDY_1, TXRDY_2, TXRDY_3, and TXRDY_4
pins. Also, this pin must be driven active before transmit FIFO writes can be
performed.
1.0 Pin Description
4-Port 84C30A
4-4
4
MD400151/C
Pin
Pin Name
I/O
Description
36
RXRDEN
I
This is an active low input that, when driven active with the RXINTEN pin, enables
read operations from one of the four receive FIFOs within the chip.
37
TXWREN
I
This is an active low input that, when driven active with the TXINTEN pin, enables
write operations to one of the four transmit FIFOs within the chip.
35
RXRD_TXWR
I
This is the system clock acting as the chip's read/write strobe to any of the
chips eight receive/transmit FIFO's. With the TXINTEN and TXWREN inputs active
low, this input becomes the write strobe for writing transmit data to one of the chip's
transmit FIFOs. Similarly, with the RXINTEN and RXRDEN inputs active low, this
input becomes the read strobe for reading receive data from one of the chips receive
FIFOs. This input must be connected to a continuous clock whose maximum
frequency can be 33 MHz.
30, 29
RXTXPS[1:0]
I
These inputs are used to select a port's receiver or transmitter for one of the following
operations:
1. Receive FIFO Reads
2. Transmit FIFO Writes
3. Clearing a TXRET Condition
4. Clearing a RXDC Condition
5. Aborting a Receive Packet
23, 24
RXTXBE[3:0]
I
These are active low inputs that determine which bytes of the double word for a
25, 26
receive FIFO read are driven with valid data or which bytes of a double word being
written to a transmit FIFO contain valid data.
44, 57
TXRDY_ [1:4]
O
These are active high three state outputs. When enabled, these outputs function as
64, 73
a flag that indicates whether the associated port's transmit FIFO has enough space
available to meet the threshold value programmed in the FIFO threshold register.
When enabled, a high value on any of these outputs indicates that the associated
port's transmit FIFO has greater than or equal to the threshold number of double word
spaces available in the FIFO and a low value indicates it does not. The tristate drivers
for all these outputs are enabled by a low value on the TXINTEN input pin.
42, 56
RXRDY_ [1:4]
O
These are active high three state outputs. When enabled, these outputs function as
63, 72
a flag that indicates whether the associated port's receive FIFO has enough data
available to meet the threshold value programmed in the FIFO threshold register.
When enabled, a high value on any of these outputs indicates that the associated
port's receive FIFO has greater than or equal to the threshold number of double
words available in the FIFO or has a completed receive packet in the FIFO as
indicated by the packets status double word being in the FIFO. The tristate drivers
for all these outputs are enabled by a low value on the RXINTEN input pin.
39
SPDTAVL
O
This is an active high output that can be used for validating reads from the receive
FIFO during a read operation and preventing over writes to the transmit FIFO during
a write operation. For further details, please refer to the Transmit Data Write timing
and the Receive Data Read timing diagrams.
40
RXTXEOF
I/O
This is a bidirectional pin that is used to signal the last double word of a transmit or
receive packet. During receive FIFO reads, this pin is enabled as an output and
when detected high indicates that the last double word of a receive packet has been
read from the receive FIFO. During transmit FIFO writes, this pin is an input and when
asserted high during a write it indicates that this is the final double word of a transmit
packet. In the transmit FIFO write case, the value of this signal is stored as the 33rd
bit in the FIFO. In the receive FIFO read case, the value of this signal is read out as
the 33rd bit of the receive FIFO.
Pin Description (cont.)
4-Port 84C30A
4-5
MD400151/C
5
Pin
Pin Name
I/O
Description
41
TXNOCRC
I
This active high input is used to control appending of a CRC to a transmit packet.
A transmit packet can be made to exclude appending a CRC value if this input is held
high during the first double word write of transmit data to the transmit FIFO.
Transmission of all packets without CRC can be done by setting bit #4 of configura-
tion register #1. It should be noted that TXNOCRC pin can be used to control CRC
encapsulation only on a per packet basis.
80-84
RXTXDATA[31:0]
I/O
This is the bidirectional 32 bit data bus for reads or writes to the chips receive or
86-89
transmit FIFO's. For receive FIFO reads it is enabled as an output with the assertion
91-94
of the RXINTEN, RXRDEN, and a low value on the RXRD_TXWR input strobe.
96-101
Otherwise it is used as an input.
107-112
115-121
Transmit and Receive Exception Indicators
48, 62
TXRET_ [1:4]
O
These are active high tristate outputs. All four of these output pins are driven by
71, 79
tristate drivers enabled by an active low being driven onto the TXINTEN input pin.
Once enabled, a high value on any of these inputs indicates that the associated port
could not complete transmission of a packet due to one of the following conditions
and that a retransmission of the packet is requested:
1. A late collision occurred during transmission.
2. Carrier sense never went high or dropped out
during transmission.
3. During a transmission attempt a transmit FIFO underflow error occurred.
4. 16 attempts to transmit the packet all resulting in transmit collisions.
Internally, the TXRET signal will remain high until it is cleared by the CLRTXERR pin,
(See the text on clearing error conditions). As long as the internal TXRET signal for
a port remains high, that port's transmit FIFO will remain cleared and no new
transmissions can occur.
45, 58
RXDC_ [1:4]
O
These are active high tristate outputs. All four of these outputs pins are driven
65, 74
by tristate drivers enabled by a low value being driven onto the RXINTEN input pin.
Once enabled, a high value on any of these inputs indicates that the associated port's
discarded reception of a packet due to one of the possible receive discard conditions.
Internally, a port's RXDC signal will remain high until it is cleared by the CLRRXERR
pin, (See the text on "Receive Discard Conditions"). As long as the internal RXDC
signal for a port remains high, that port's receive FIFO will remain cleared and no new
packets will be received.
Special Purpose Pins
38
CLRTXERR
I
This active high input is used to clear transmit retry flags within the chip. See the
"Receive Discard Conditions" section for how this input is used.
50
CLRRXERR
I
This active high input is used to clear Receive Discard flags within the chip. See the
"Receive Discard Conditions" section for how this input is used.
46
RXABORT_1
I
This input when pulsed high causes port #1 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
59
RXABORT_2
I
This input when pulsed high causes port #2 to abort reception of a receive frame and
clear the Receive FIFO. It can be asserted at any time during the reception of a
frame.
Pin Description (cont.)
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