MD400177/B
84220
1
Features
s
Single Chip 100BaseTX/100BaseFX/10BaseT
Physical Layer Solution
s
Four Independent Channels in One IC
s
3.3V Power Supply with 5V Tolerant I/O
s
Dual Speed - 10/100 Mbps
s
Half and Full Duplex
s
MII Interface or Reduced Pin Count MII (RMII)
Interface to Ethernet Controller
s
MI Interface for Configuration and Status
s
Optional Repeater Interface
s
AutoNegotiation for 10/100, Full/Half Duplex
s
Meets all Applicable IEEE 802.3, 10BaseT,
100BaseTX and 100BaseFX Standards
s
On Chip Wave Shaping - No External Filters
Required
s
Adaptive Equalizer for 100BaseTX
s
Baseline Wander Correction
s
LED Outputs
Link
Activity
Collision
Full Duplex
Far End Fault (for FX)
10/100
s
160L PQFP
Description
The 84220 is a highly integrated Ethernet Transceiver for
twisted pair and fiber Ethernet applications. The 84220
can be configured for either 100 Mbps (100BaseFX or
100BaseTX) or 10 Mbps (10BaseT) Ethernet operation.
The 84220 consists of four (4) separate and independent
channels. Each channel consists of: 4B5B/Manchester
encoder, scrambler, transmitter with wave shaping and on-
chip filters, transmit output driver, receiver with adaptive
equalizer, filters, baseline wander correction, clock and
data recovery, descrambler, 4B5B/Manchester decoder,
and controller interface (MII or RMII).
The addition of internal output waveshaping circuitry and
on-chip filters eliminates the need for external filters
normally required in 100BaseTX and 10BaseT
applications.
The 84220 can automatically configure itself for 100 or 10
Mbps and Full or Half Duplex operation, for each channel
independently, using the on-chip AutoNegotiation
algorithm.
The 84220 can access eleven 16-bit registers for each
channel through the Management Interface (MI) serial
port. These registers comply to Clause 22 of IEEE 802.3u
and contain configuration inputs, status outputs, and
device capabilities.
The 84220 is ideal as a media interface for 100BaseTX/
100BaseFX/10BaseT switching hubs, repeaters, routers,
bridges, and other multi port applications.
The 84220 is implemented in a low power CMOS
technology and operates with a 3.3V power supply.
84220
99036
Note: Check for latest Data Sheet revision before
starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com
This document is an LSI Logic document. Any
reference to SEEQ Technology should be consid-
ered LSI Logic.
Quad 100BaseTX/100BaseFX/10BaseT
Physical Layer Device
4
MD400177/B
84220
1.0 PIN DESCRIPTION (cont'd)
Media Interface
Pin #
Pin Name
I/O
Description
126
136
145
155
TPOP_[3:0]/
FXIN_[3:0]
I/O
Twisted Pair Transmit Output, Positive.
Fiber Receive Input, Negative.
129
133
148
152
TPON_[3:0]/
FXIP_[3:0]
I/O
Twisted Pair Transmit Output, Negative.
Fiber Receive Input, Positive.
123
139
142
158
TPIP_[3:0]/
FXOP_[3:0]
I/O
Twisted Pair Receive Input, Positive.
Fiber Transmit Output, Positive.
124
138
143
157
TPIN_[3:0]/
FXON_[3:0]
I/O
Twisted Pair Receive Input, Negative.
Fiber Transmit Output, Negative.
130
137
149
156
SD_[3:0]/
FXEN_[3:0]
I
Fiber Interface Signal Detect Input.
Fiber Interface Enable.
When this pin in not tied to GND, the fiber interface is enabled and this pin
becomes a Signal Detect ECL input. The trip point for this ECL input is
determined by the voltage applied to the SD_THR pin. When this pin is tied
to GND, the fiber interface is disabled (i.e. TP Interface is enabled).
159
SD_THR
---
Fiber Interface Signal Detect Threshold Reference.
The voltage applied
to this pin sets the reference level for the fiber interface SD input pin so that
the device can directly connect SD pin to both 3.3V and 5V fiber optic
tansceivers. Typically, this pin is either tied to GND (for 3.3V) or to an
external voltage divider (for 5V).
140
REXT
---
Transmit Current Set.
An external resistor connected between this pin and GND will set the level
for the transmit outputs.
MD400177/B
84220
5
1.0 PIN DESCRIPTION (cont'd)
Controller Interface (MII & RMII)
Pin #
Pin Name
I/O
Description
87
69
50
31
TXCLK_[3:0]
O
Transmit Clock Output.
These interface outputs provide clocks to external
controllers. Transmit data from the controller on TXD, TXEN, and TXER is
clocked in on the rising edges of TXCLK and CLKIN.
88
70
51
32
TXEN_[3:0]
I
Transmit Enable Input.
These interface inputs must be be asserted active
high to allow data on TXD and TXER to be clocked in on the rising edges of
TXCLK and CLKIN.
[92:89]
[74:71]
[55:52]
[36:33]
TXD[3:0]_3
TXD[3:0]_2
TXD[3:0]_1
TXD[3:0]_0
I
Transmit Data Input.
These interface inputs contain input nibble data to be
transmitted on the TP or FX outputs and are clocked in on rising edges of
TXCLK and CLKIN. In RMII mode, only TXD[1:0] are used.
86
68
49
30
TXER_[3:0]/
TXD4_[3:0]
I
Transmit Error Input.
These interface inputs initiate an error pattern to be
transmitted on the TP or FX outputs and are clocked in on rising edges of
TXCLK when TXEN is asserted.
If the channel is placed in the Bypass 4B5B Encoder mode, these pins are
reconfigured to be the fifth TXD transmit data input, TXD4. In RMII mode,
these pins are not used.
84
66
47
28
RXCLK_[3:0]
O
Receive Clock Output.
These interface outputs provide a clock to the
controller. Receive data on RXD, RXDV, and RXER is clocked out to the
controller on falling edges of RXCLK.
94
76
58
38
CRS_[3:0]
O
Carrier Sense Output.
These interface outputs are asserted active high
when valid data is detected on the receive TP or FX inputs and is clocked
out on the falling edge of RXCLK.
83
65
46
27
RXDV_[3:0]
O
Receive Data Valid Output.
These interface outputs are asserted active
high when valid decoded data is present on the RXD outputs and is clocked
out on falling edges of RXCLK. In RMII mode, these pins are not used.
[79:82]
[61:64]
[42:45]
[23:26]
RXD[3:0]_3
RXD[3:0]_2
RXD[3:0]_1
RXD[3:0]_0
O
Receive Data Output.
These interface outputs contain recovered nibble
data from the TP or FX inputs and are clocked out on the falling edges of
RXCLK. In RMII mode, only RXD[1:0] are used.
85
67
48
29
RXER_[3:0]/
RXD4_[3:0]
O
Receive Error Output.
These interface outputs are asserted active high
when coding or other specified errors are detected on the TP or FX inputs
and are clocked out on falling edges of RXCLK.
If the channel is placed in the Bypass 4B5B Decoder mode, these pins are
reconfigured to be the fifth RXD receive data output, RXD4.
93
75
57
37
COL_[3:0]
O
Collision Output.
These interface outputs are asserted active high when
collision between transmit and receive data is detected.
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