Document Outline

• Chapter1 General Description
  • Figure1.1 Typical LSI53C876 System Application
  • Figure1.2 Typical LSI53C876 Board Application
  • 1.1 Wide Ultra SCSI Benefits
  • 1.2 TolerANT� Technology
  • 1.3 LSI53C876 Benefits
    • 1.3.1 PCI Performance
    • 1.3.2 SCSI Performance
    • 1.3.3 Testability
    • 1.3.4 Integration
    • 1.3.5 Reliability
• Chapter2 Functional Description
  • Figure2.1 LSI53C876 Block Diagram
  • 2.1 PCI Functional Description
    • 2.1.1 PCI Addressing
      • 2.1.1.1 Configuration Space
    • 2.1.2 PCI Bus Commands and Functions Supported
      • Table 2.1 PCI Bus Commands and Encoding Types
      • 2.1.2.1 Interrupt Acknowledge Command
      • 2.1.2.2 Special Cycle Command
      • 2.1.2.3 I/O Read Command
      • 2.1.2.4 I/O Write Command
      • 2.1.2.5 Reserved Command
      • 2.1.2.6 Memory Read Command
      • 2.1.2.7 Memory Write Command
      • 2.1.2.8 Configuration Read Command
      • 2.1.2.9 Configuration Write Command
      • 2.1.2.10 Memory Read Multiple Command
      • 2.1.2.11 Dual Address Cycles (DACs) Command
      • 2.1.2.12 Memory Read Line Command
      • 2.1.2.13 Memory Write and Invalidate Command
    • 2.1.3 Internal Arbiter
    • 2.1.4 PCI Cache Mode
      • 2.1.4.1 Selection of Cache Line Size
      • 2.1.4.2 Alignment
      • 2.1.4.3 Memory Move Misalignment
  • 2.2 SCSI Functional Description
    • 2.2.1 Two SCSI Controllers
    • 2.2.2 SCRIPTS Processor
      • 2.2.2.1 Internal SCRIPTS RAM
      • 2.2.2.2 Prefetching SCRIPTS Instructions
      • 2.2.2.3 OpCode Fetch Burst Capability
      • 2.2.2.4 Load/Store Instructions
    • 2.2.3 JTAG Boundary Scan Testing
    • 2.2.4 SCSI Loopback Mode
    • 2.2.5 Parity Options
      • Table 2.2 Bits Used for Parity Control and Generation
      • Table 2.3 SCSI Parity Control
      • Table 2.4 SCSI Parity Errors and Interrupts
      • Figure2.2 Parity Checking/Generation
    • 2.2.6 DMA FIFO
      • Figure2.3 DMA FIFO Sections
      • 2.2.6.1 Data Paths
        • Figure2.4 LSI53C876 Host Interface SCSI Data Paths
    • 2.2.7 SCSI Bus Interface
      • 2.2.7.1 Differential Mode
        • Table 2.5 Differential Mode
        • Figure2.5 LSI53C876 Differential Wiring Diagram
      • 2.2.7.2 Terminator Networks
        • Figure2.6 Regulated Termination
    • 2.2.8 Synchronous Operation
      • 2.2.8.1 Determining the Data Transfer Rate
      • 2.2.8.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0])
      • 2.2.8.3 SCSI Control Three (SCNTL3) Register, Bits [2:0] (CCF[2:0]
      • 2.2.8.4 SCSI Transfer (SXFER) Register, Bits [7:5] (TP[2:0])
      • 2.2.8.5 Wide Ultra SCSI Synchronous Transfers
        • Figure2.7 Determining the Synchronous Transfer Rate
    • 2.2.9 Designing a Wide Ultra SCSI System
    • 2.2.10 Interrupt Handling
      • 2.2.10.1 Polling and Hardware Interrupts
      • 2.2.10.2 Registers
      • 2.2.10.3 Fatal vs. Nonfatal Interrupts
      • 2.2.10.4 Masking
      • 2.2.10.5 Stacked Interrupts
      • 2.2.10.6 Halting in an Orderly Fashion
      • 2.2.10.7 Sample Interrupt Service Routine
    • 2.2.11 Chained Block Moves
      • Figure2.8 Block Move and Chained Block Move Instructions
      • 2.2.11.1 Wide SCSI Send Bit
      • 2.2.11.2 Wide SCSI Receive Bit
      • 2.2.11.3 SWIDE Register
      • 2.2.11.4 SODL Register
      • 2.2.11.5 Chained Block Move SCRIPTS Instruction
  • 2.3 Parallel ROM Interface
    • Table 2.6 Parallel ROM Support
  • 2.4 Serial EEPROM Interface
    • 2.4.1 Mode A Operation
      • Table 2.7 Mode A Serial EEPROM Data Format
    • 2.4.2 Mode B Operation
    • 2.4.3 Mode C Operation
      • Table 2.8 Mode C Serial EEPROM Data Format
    • 2.4.4 Mode D Operation
  • 2.5 Power Management
    • Table 2.9 Power States
    • 2.5.1 Power State D0
    • 2.5.2 Power State D1
    • 2.5.3 Power State D2
    • 2.5.4 Power State D3
• Chapter3 Signal Descriptions
  • Figure3.1 LSI53C876 208-Pin PQFP Diagram
  • Figure3.2 LSI53C876 256-Ball BGA Diagram (Top View)
  • Figure3.3 LSI53C876 Functional Signal Grouping
  • 3.1 PCI Interface Signals
    • 3.1.1 System Signals
      • Table 3.1 System Signals
    • 3.1.2 Address and Data Signals
      • Table 3.2 Address and Data Signals
    • 3.1.3 Interface Control Signals
      • Table 3.3 Interface Control Signals
    • 3.1.4 Arbitration Signals
      • Table 3.4 Arbitration Signals
    • 3.1.5 Error Reporting Signals
      • Table 3.5 Error Reporting Signals
    • 3.1.6 PCI Interrupt Signals
      • Table 3.6 PCI Interrupt Signals
    • 3.1.7 GPIO Interface Signals
      • Table 3.7 SCSI GPIO Function A Signals
      • Table 3.8 SCSI GPIO Function B Signals 
  • 3.2 SCSI Bus Interface Signals
    • 3.2.1 SCSI Bus Interface Signal
      • Table 3.9 SCSI Bus Interface Signal
    • 3.2.2 SCSI Bus Interface
      • Table 3.10 SCSI Function A Interface Signals
      • Table 3.11 SCSI Function B Interface Signals 
      • Table 3.12 SCSI Function A Differential Control Signals 
      • Table 3.13 SCSI Function B Differential Control Signals
  • 3.3 ROM/Flash Interface Signals
    • Table 3.14 ROM/Flash Interface Signals
  • 3.4 Test Interface Signals
    • Table 3.15 Test Interface Signals
  • 3.5 Power and Ground Signals
    • Table 3.16 Power and Ground Signals
    • 3.5.1 Isolated Power Supplies
  • 3.6 MAD Bus Programming
    • Table 3.17 Decode of MAD Pins
• Chapter4 Registers
  • 4.1 PCI Configuration Registers
    • Table 4.1 PCI to SCSI Configuration Register Map
  • 4.2 SCSI Registers
    • Table 4.2 LSI53C876 SCSI Register Address Map
    • Table 4.3 Examples of Synchronous Transfer Periods for SCSI-1 Transfer Rates
    • Table 4.4 Example Transfer Periods for Fast SCSI and Wide Ultra SCSI Transfer Rates
    • Table 4.5 Maximum Synchronous Offset
    • Table 4.6 SCSI Synchronous Data FIFO Word Count
• Chapter5 SCSI SCRIPTS Instruction Set
  • 5.1 Low Level Register Interface Mode
  • 5.2 High Level SCSI SCRIPTS Mode
    • Table 5.1 SCRIPTS Instructions
    • 5.2.1 Sample Operation
      • Figure5.1 SCRIPTS Overview
  • 5.3 Block Move Instruction
    • 5.3.1 First Dword
      • Figure5.2 Block Move Instruction Register
    • 5.3.2 Second Dword
  • 5.4 I/O Instruction
    • 5.4.1 First Dword
      • Figure5.3 I/O Instruction Register
    • 5.4.2 Second Dword
  • 5.5 Read/Write Instructions
    • 5.5.1 First Dword
      • Figure5.4 Read/Write Instruction Register
    • 5.5.2 Second Dword
    • 5.5.3 Read-Modify-Write Cycles
    • 5.5.4 Move To/From SFBR Cycles
      • Table 5.2 Read/Write Instructions
  • 5.6 Transfer Control Instructions
    • 5.6.1 First Dword
      • Figure5.5 Transfer Control Instruction
    • 5.6.2 Second Dword
  • 5.7 Memory Move Instructions
    • 5.7.1 Read/Write System Memory from SCRIPTS
    • 5.7.2 Second Dword
    • 5.7.3 Third Dword
      • Figure5.6 Memory Move Instruction
  • 5.8 Load and Store Instructions
    • 5.8.1 First Dword
    • 5.8.2 Second Dword
      • Figure5.7 Load and Store Instruction Format
• Chapter6 Electrical Characteristics
  • 6.1 DC Characteristics
    • Table 6.1 Absolute Maximum Stress Ratings
    • Table 6.2 Operating Conditions
    • Table 6.3 SCSI Signals�SD[15:0]/, SDP[1:0]/, SREQ/, SACK/
    • Table 6.4 SCSI Signals�SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
    • Table 6.5 Input Signals�CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS
    • Table 6.6 Capacitance
    • Table 6.7 Output Signals�INTA/, INTB/
    • Table 6.8 Output Signals�SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0],...
    • Table 6.9 Output Signal�REQ/
    • Table 6.10 Output Signal�SERR/
    • Table 6.11 Bidirectional Signals�AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR...
    • Table 6.12 Bidirectional Signals�GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4
    • Table 6.13 Bidirectional Signals�MAD[7:0]
    • Table 6.14 Input Signals�TDI, TMS, TCK
    • Table 6.15 Output Signal�TDO
  • 6.2 3.3 V PCI DC Characteristics
    • Table 6.16 Bidirectional Signals�AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR...
    • Table 6.17 Input Signals�CLK, GNT/, IDSEL, RST/,
    • Table 6.18 Output Signals�INTA/, INTB, REQ/
    • Table 6.19 Output Signal�SERR/
  • 6.3 TolerANT Technology Electrical Characteristics
    • Table 6.20 TolerANT Technology Electrical Characteristics
    • Figure6.1 Rise and Fall Time Test Conditions
    • Figure6.2 SCSI Input Filtering
    • Figure6.3 Hysteresis of SCSI Receivers
    • Figure6.4 Input Current as a Function of Input Voltage
    • Figure6.5 Output Current as a Function of Output Voltage
  • 6.4 AC Characteristics
    • Table 6.21 Clock Timing
    • Figure6.6 Clock Timing
    • Table 6.22 Reset Input
    • Figure6.7 Reset Input
    • Table 6.23 Interrupt Output
    • Figure6.8 Interrupt Output
    • 6.4.1 PCI and External Memory Interface Timings
      • 6.4.1.1 3.3 V PCI Timings
        • Table 6.24 3.3 V PCI Timing
        • Table 6.25 Configuration Register Read
        • Figure6.9 Configuration Register Read
        • Table 6.26 Configuration Register Write
        • Figure6.10 Configuration Register Write
        • Table 6.27 Target Read (Not From External Memory)
        • Figure6.11 Target Read (Not From External Memory)
        • Table 6.28 Target Write (Not From External Memory)
        • Figure6.12 Target Write (Not From External Memory)
        • Table 6.29 Target Read (From External Memory)
        • Figure6.13 Target Read, from External Memory
        • Table 6.30 Target Write (From External Memory)
        • Figure6.14 Target Write, from External Memory
        • Table 6.31 Opcode Fetch, Nonburst
        • Figure6.15 Opcode Fetch, Nonburst
        • Table 6.32 Opcode Fetch, Burst
        • Figure6.16 Opcode Fetch, Burst
        • Table 6.33 Back-to-Back Read
        • Figure6.17 Back-to-Back Read
        • Table 6.34 Back-to-Back Write
        • Figure6.18 Back-to-Back Write
        • Table 6.35 Burst Read
        • Figure6.19 Burst Read
        • Table 6.36 Burst Write
        • Figure6.20 Burst Write
        • Table 6.37 Read Cycle, Norma/Fast Memory (� 128 Kbytes), Single Byte Access
        • Figure6.21 Read Cycle, Normal/Fast Memory (� 128 Kbytes), Single Byte Access
        • Table 6.38 Write Cycle, Normal/Fast Memory (� 128 Kbytes), Single Byte Access
        • Figure6.22 Write Cycle, Normal/Fast Memory (� 128 Kbytes), Single Byte Access
        • Figure6.23 Read Cycle, Normal/Fast Memory (� 128 Kbyte), Multiple Byte Access
        • Figure6.24 Write Cycle, Normal/Fast Memory (� 128 Kbyte), Multiple Byte Access
        • Table 6.39 Read Cycle, Slow Memory (� 128 Kbytes)
        • Figure6.25 Read Cycle, Slow Memory (� 128 Kbytes)
        • Table 6.40 Write Cycle, Slow Memory (� 128 Kbytes)
        • Figure6.26 Write Cycle, Slow Memory (� 128 Kbytes)
        • Figure6.27 Read Cycle, 16 Kbytes ROM
        • Figure6.28 Read Cycle, 16 Kbytes ROM
        • Table 6.41 Write Cycle, 16 Kbytes ROM
        • Figure6.29 Write Cycle, 16 Kbytes ROM
    • 6.4.2 PCI and External Memory Interface Timing
      • Table 6.42 LSI53C876 PCI and External Memory Interface Timing
    • 6.4.3 SCSI Interface Timing
      • Table 6.43 Initiator Asynchronous Send
      • Figure6.30 Initiator Asynchronous Send
      • Table 6.44 Initiator Asynchronous Receive
      • Figure6.31 Initiator Asynchronous Receive
      • Table 6.45 Target Asynchronous Send
      • Figure6.32 Target Asynchronous Send
      • Table 6.46 Target Asynchronous Receive
      • Figure6.33 Target Asynchronous Receive
      • Figure6.34 Initiator and Target Synchronous Transfers
      • Table 6.47 SCSI-1 Transfers (SE, 5.0 Mbytes/s)
      • Table 6.48 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transf...
      • Table 6.49 SCSI-2 Fast-20 SE Transfers (20.0 Mbytes/s (8-Bit Transfers) or 40.0Mbytes/s (16-Bit ...
  • 6.5 Package Diagrams
    • Figure6.35 256-pin PBGA (GU) Mechanical Drawing
    • Figure6.36 208-pin PQFP (P9) Mechanical Drawing (Sheet 1 of 2)
• AppendixA Register Summary
  • TableA.1 Configuration Registers (Cont.)
  • TableA.2 SCSI Registers (Cont.)
• AppendixB External Memory Interface Diagram Examples
  • FigureB.1 64 Kbyte Interface with 200 ns Memory
  • FigureB.2 64 Kbyte Interface with 150 ns Memory
  • FigureB.3 256 Kbyte Interface with 150 ns Memory
  • FigureB.4 512 Kbyte Interface with 150 ns Memory
• Index
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