Document Outline

• LSI53C875/875E PCI to Ultra SCSI I/O Processor
  • Chapter1 General Description
    • Figure1.1 LSI53C875 External Memory Interface
    • Figure1.2 LSI53C875 Chip Block Diagram
  • 1.1 Package and Feature Options
  • 1.2 Benefits of Ultra SCSI
  • 1.3 TolerANT� Technology
  • 1.4 LSI53C875 Benefits Summary
    • 1.4.1 SCSI Performance
    • 1.4.2 PCI Performance
    • 1.4.3 Integration
    • 1.4.4 Ease of Use
    • 1.4.5 Flexibility
    • 1.4.6 Reliability
    • 1.4.7 Testability
  • Chapter2 Functional Description
  • 2.1 SCSI Functional Description
    • 2.1.1 SCSI Core
    • 2.1.2 DMA Core
    • 2.1.3 SCRIPTS Processor
    • 2.1.4 Internal SCRIPTS RAM
    • 2.1.5 SDMS Software: The Total SCSI Solution
  • 2.2 Designing an Ultra SCSI System
    • 2.2.1 Using the SCSI Clock Doubler
  • 2.3 Prefetching SCRIPTS Instructions
    • 2.3.1 Opcode Fetch Burst Capability
  • 2.4 External Memory Interface
    • Table 2.1 External Memory Support
  • 2.5 PCI Cache Mode
    • 2.5.1 Load/Store Instructions
    • 2.5.2 3.3 V/5 V PCI Interface
    • 2.5.3 Additional Access to General Purpose Pins
    • 2.5.4 JTAG Boundary Scan Testing
    • 2.5.5 Big and Little Endian Support
    • 2.5.6 Loopback Mode
    • 2.5.7 Parity Options
      • Table 2.2 Bits Used for Parity Control and Generation
      • Table 2.3 SCSI Parity Control
      • Table 2.4 SCSI Parity Errors and Interrupts
    • 2.5.8 DMA FIFO
      • Figure2.1 DMA FIFO Sections
      • Figure2.2 LSI53C875 Host Interface Data Paths
    • 2.5.9 SCSI Bus Interface
      • Table 2.5 Differential Mode
      • Figure2.3 Differential Wiring Diagram
      • Figure2.4 Regulated Termination
    • 2.5.10 Select/Reselect During Selection/Reselection
    • 2.5.11 Synchronous Operation
      • Figure2.5 Determining the Synchronous Transfer Rate
    • 2.5.12 Ultra SCSI Synchronous Data Transfers
    • 2.5.13 Interrupt Handling
    • 2.5.14 Chained Block Moves
      • Figure2.6 Block Move and Chained Block Move Instructions
  • 2.6 Power Management
    • 2.6.1 Power State D0
    • 2.6.2 Power State D3
  • Chapter3 PCI Functional Description
  • 3.1 PCI Addressing
    • 3.1.1 PCI Bus Commands and Functions Supported
      • Table 3.1 PCI Bus Commands and Encoding Types
  • 3.2 PCI Cache Mode
    • 3.2.1 Support for PCI Cache Line Size Register
    • 3.2.2 Selection of Cache Line Size
    • 3.2.3 Alignment
    • 3.2.4 Memory Move Misalignment
    • 3.2.5 Memory Write and Invalidate Command
    • 3.2.6 Memory Read Line Command
    • 3.2.7 Memory Read Multiple Command
  • 3.3 Configuration Registers
    • Table 3.2 PCI Configuration Register Map
  • Chapter4 Signal Descriptions
    • Figure4.1 LSI53C875 Pin Diagram
    • Figure4.2 LSI53C875J Pin Diagram
    • Figure4.3 LSI53C875N Pin Diagram
    • Figure4.4 LSI53C875JB Pin Diagram (Top View)
      • Table 4.1 LSI53C875, LSI53C875J, LSI53C875E, and LSI53C875JE Power and Ground Signals
      • Table 4.2 LSI53C875N Power and Ground Signals
      • Table 4.3 LSI53C875JB and LSI53C875JBE Power and Ground Signals
    • Figure4.5 LSI53C875 Functional Signal Grouping
      • Table 4.4 System Signals
      • Table 4.5 Address and Data Signals
      • Table 4.6 Interface Control Signals
      • Table 4.7 Arbitration Signals
      • Table 4.8 Error Reporting Signals
      • Table 4.9 SCSI SIgnals
      • Table 4.10 Additional Interface Signals
      • Table 4.11 External Memory Interface Signals
      • Table 4.12 JTAG Signals (LSI53C875J/LSI53C875N/LSI53C875JB Only)
  • 4.1 MAD Bus Programming
    • Table 4.13 Subsystem Data Configuration Table for the LSI53C875E (PCI Rev ID 0x26)
    • Table 4.14 Subsystem Data Configuration Table for the LSI53C875 (PCI Rev ID 0x04), Revision G Only
    • Table 4.15 External Memory Support
  • Chapter5 SCSI Operating Registers
    • Table 5.1 LSI53C875 Register Map
    • Table 5.2 Examples of Synchronous Transfer Periods for SCSI-1 Transfer Rates
    • Table 5.3 Example Transfer Periods for Fast SCSI-2 and Ultra SCSI Transfer Rates
    • Table 5.4 Maximum Synchronous Offset
    • Table 5.5 SCSI Synchronous Data FIFO Word Count
  • Chapter6 Instruction Set of the I/O Processor
  • 6.1 SCSI SCRIPTS
    • Table 6.1 SCRIPTS Instructions
    • 6.1.1 Sample Operation
      • Figure6.1 SCRIPTS Overview
  • 6.2 Block Move Instructions
    • 6.2.1 First Dword
      • Figure6.2 Block Move Instruction Register
    • 6.2.2 Second Dword
  • 6.3 I/O Instruction
    • 6.3.1 First Dword
      • Figure6.3 I/O Instruction Register
    • 6.3.2 Second Dword
  • 6.4 Read/Write Instructions
    • 6.4.1 First Dword
    • 6.4.2 Second Dword
    • 6.4.3 Read-Modify-Write Cycles
      • Figure6.4 Read/Write Instruction Register
    • 6.4.4 Move To/From SFBR Cycles
      • Table 6.2 Read/Write Instructions
  • 6.5 Transfer Control Instructions
    • 6.5.1 First Dword
      • Figure6.5 Transfer Control Instructions
    • 6.5.2 Second Dword
  • 6.6 Memory Move Instructions
    • 6.6.1 Read/Write System Memory from SCRIPTS
    • 6.6.2 Second Dword
    • 6.6.3 Third Dword
      • Figure6.6 Memory Move Instruction
  • 6.7 Load and Store Instructions
    • 6.7.1 First Dword
    • 6.7.2 Second Dword
      • Figure6.7 Load and Store Instruction Format
  • Chapter7 Instruction Set of the I/O Processor
  • 7.1 DC Characteristics
    • Table 7.1 Absolute Maximum Stress Ratings
    • Table 7.2 Operating Conditions
    • Table 7.3 SCSI Signals�SD[15:0]/, SDP[1:0]/, SREQ/, SACK/
    • Table 7.4 SCSI Signals�SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
    • Table 7.5 Input Signals�CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS, BIG_LIT/
    • Table 7.6 Capacitance
    • Table 7.7 Output Signals�MAC/_TESTOUT, REQ/
    • Table 7.8 Output Signals�IRQ/, SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/...
    • Table 7.9 Output Signal�SERR/
    • Table 7.10 Bidirectional Signals�AD[31:0], C_BE[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...
    • Table 7.11 Bidirectional Signals�GPIO0_FETCH/, GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4
    • Table 7.12 Bidirectional Signals�MAD[7:0]
    • Table 7.13 Input Signals�TDI, TMS, TCK (LSI53C875J, LSI53C875JB, LSI53C875N Only)
    • Table 7.14 Output Signal�TDO (LSI53C875, LSI53C875JB, LSI53C875N Only)
  • 7.2 TolerANT Technology Electrical Characteristics
    • Table 7.15 TolerANT Technology Electrical Characteristics
    • Figure7.1 Rise and Fall Time Test Conditions
    • Figure7.2 SCSI Input Filtering
    • Figure7.3 Hysteresis of SCSI Receiver
    • Figure7.4 Input Current as a Function of Input Voltage
    • Figure7.5 Output Current as Function of Output Voltage
  • 7.3 AC Characteristics
    • Table 7.16 Clock Timing
    • Figure7.6 Clock Waveforms
      • Table 7.17 Reset Input
    • Figure7.7 Reset Input
      • Table 7.18 Interrupt Output
    • Figure7.8 Interrupt Output
  • 7.4 PCI and External Memory Interface Timing Diagrams
    • 7.4.1 Target Timing
      • Figure7.9 PCI Configuration Register Read
      • Figure7.10 PCI Configuration Register Write
      • Figure7.11 Operating Register/SCRIPTS RAM Read
      • Figure7.12 Operating Register/SCRIPTS RAM Write
      • Figure7.13 External Memory Read
      • Figure7.14 External Memory Write
    • 7.4.2 Initiator Timing
      • Figure7.15 Opcode Fetch, Nonburst
      • Figure7.16 Burst Opcode Fetch
      • Figure7.17 Back-to-Back Read
      • Figure7.18 Back-to-Back Write
      • Figure7.19 Burst Read
      • Figure7.20 Burst Write
    • 7.4.3 External Memory Timing
      • Figure7.21 Read Cycle, Normal/Fast Memory (� 64 Kbytes), Single Byte Access
      • Figure7.22 Write Cycle, Normal/Fast Memory (� 64 Kbytes), Single Byte Access
      • Figure7.23 Read Cycle, Normal/Fast Memory (� 64 Kbyte), Multiple Byte Access
      • Figure7.24 Write Cycle, Normal/Fast Memory (� 64 Kbyte), Multiple Byte Access
      • Figure7.25 Read Cycle, Slow Memory (� 64 Kbyte)
      • Figure7.26 Write Cycle, Slow Memory (� 64 Kbyte)
      • Figure7.27 Read Cycle, Normal/Fast Memory (� 64 Kbyte)
      • Figure7.28 Write Cycle, Normal/Fast Memory (� 64 Kbyte)
      • Figure7.29 Read Cycle, Slow Memory (� 64 Kbyte)
      • Figure7.30 Write Cycle, Slow Memory (� 64 Kbyte)
  • 7.5 PCI and External Memory Interface Timing
    • Table 7.19 LSI53C875 PCI and External Memory Interface Timing
  • 7.6 SCSI Timing Diagrams
    • Table 7.20 Initiator Asynchronous Send
    • Figure7.31 Initiator Asynchronous Send
      • Table 7.21 Initiator Asynchronous Receive
    • Figure7.32 Initiator Asynchronous Receive
      • Table 7.22 Target Asynchronous Send
    • Figure7.33 Target Asynchronous Send
      • Table 7.23 Target Asynchronous Receive
    • Figure7.34 Target Asynchronous Receive
    • Figure7.35 Initiator and Target Synchronous Transfer
      • Table 7.24 SCSI-1 Transfers (SE, 5.0 Mbytes/s)
      • Table 7.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s)
      • Table 7.26 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfe...
      • Table 7.27 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transfe...
      • Table 7.28 Ultra SCSI SE Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Trans...
      • Table 7.29 Ultra SCSI Differential Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0Mbytes/s (16...
  • 7.7 Package Drawings
    • Figure7.36 169-Pin PBGA (GV) Mechanical Drawing
    • Figure7.37 160-pin PQFP (P3) Mechanical Drawing (Sheet 1 of 2)
  • AppendixA Register Summary
    • TableA.1 Configuration Registers
    • TableA.2 LSI53C875 Register Map
  • AppendixB External Memory Interface Diagram Examples
    • FigureB.1 64 Kbyte Interface with 200 ns Memory
    • FigureB.2 64 Kbyte Interface with 150 ns Memory
    • FigureB.3 256 Kbyte Interface with 150 ns Memory
    • FigureB.4 512 Kbyte Interface with 150 ns Memory
  • Index
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