MD400183/B
April, 2002
1 of 118
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
L84225 100BaseTX/FX/10BaseT
Physical Layer Device
Technical Manual
Features
Note:
Check for the latest revision of this document before start-
ing any designs. This document is available on the Web, at
www.lsilogic.com
Single-chip 100BaseTX/100BaseFX/
10BaseT physical layer solution
Four independent Channels in One IC
3.3 V power supply with 5 V tolerant I/O
Dual Speed - 10/100 Mbps
Half and Full Duplex
MII interface or reduced pin count MII
(RMII) interface to Ethernet Controller
MI interface for configuration and status
Optional Repeater Interface
AutoNegotiation for 10/100, Full/Half
Duplex hardware controlled
advertisement
Meets all applicable IEEE 802.3,
10BaseT, 100BaseTX and 100BaseFX
standards
On-chip wave shaping - no external
filters required
Adaptive Equalizer for 100BaseTX
Baseline Wander Correction
LED outputs
Link, Activity, Collision
Full Duplex
Far End Fault (for FX)
10/100
160L PQFP
Contents
Description
- - - - - - - - - - - - - - - - - - - - - 2
Pin Description
- - - - - - - - - - - - - - - - - - 4
Functional Description
- - - - - - - - - - - - -13
Register Description
- - - - - - - - - - - - - - -57
Application Information
- - - - - - - - - - - - -70
Specifications
- - - - - - - - - - - - - - - - - - - 87
Ordering Information
- - - - - - - - - - - - - 114
Revision History
- - - - - - - - - - - - - - - - 114
Surface Mount Packages
- - - - - - - - - - 117
2 of 118
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
April, 2002
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
Description
The L84225 is a highly integrated Ethernet Transceiver for twisted pair
and fiber Ethernet applications. The L84225 can be configured for either
100 Mbps (100BaseFX or 100BaseTX) or 10 Mbps (10BaseT) Ethernet
operation.
The L84225 consists of four (4) separate and independent channels.
Each channel consists of: 4B5B/Manchester encoder, scrambler,
transmitter with wave shaping and on-chip filters, transmit output driver,
receiver with adaptive equalizer, filters, baseline wander correction, clock
and data recovery, descrambler, 4B5B/Manchester decoder, and
controller interface (MII or RMII).
The addition of internal output waveshaping circuitry and on-chip filters
eliminates the need for external filters normally required in 100BaseTX
and 10BaseT applications.
The L84225 can automatically configure itself for 100 or 10 Mbps and
Full or Half Duplex operation, for each channel independently, using the
on-chip AutoNegotiation algorithm.
The L84225 can access eleven 16-bit registers for each channel through
the Management Interface (MI) serial port. These registers comply with
Clause 22 of IEEE 802.3u and contain configuration inputs, status
outputs, and device capabilities.
The L84225 is ideal as a media interface for 100BaseTX/
100BaseFX/10BaseT switching hubs, repeaters, routers, bridges, and
other multi port applications.
The L84225 is implemented in a low power CMOS technology and
operates with a 3.3V power supply.
Description
3 of 118
April, 2002
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
Pin Configuration
131
121
124
125
126
127
128
129
130
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
122
123
109
117
116
115
114
113
112
111
110
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
119
118
120
LED0_3
LED1_3
LED2_3
LED0_2
LED1_2
LED2_2
GND
LED0_1
LED1_1
LED2_1
LED0_0
LED1_0
LED2_0
GND
VDD
VDD
AD_REV
PHYAD2
PHYAD3
PHYAD4
GND
VDD
RXD3_0
RXD2_0
RXD1_0
RXD0_0
RXDV_0
RXCLK_0
RXER_0/RXD4_0
TXER_0/TXD4_0
TXCLK_0
TXEN_0
TXD0_0
TXD1_0
TXD2_0
TXD3_0
COL_0
CRS_0
GND
VDD
12
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
51
41
44
45
46
47
48
49
50
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
2
3
1
42
43
L84225
160 PQFP
Top View
SPEED_3
SPEED_2
CLKIN
LED3_3
LED3_2
LED3_1
LED3_0
SPEED_1
SPEED_0
ANEG
LEDDEF
RESET
GND
VDD
DPLX_0
DPLX_1
DPLX_2
DPLX_3
REPEATER
RMII_EN
VDD
MDC
REGDEF
MDIO
VDD
GND
CRS_3
COL_3
TXD3_3
TXD2_3
TXD1_3
TXD0_3
TXEN_3
TXCLK_3
TXER_3/TXD4_3
RXER_3/RXD4_3
RXCLK_3
RXDV_3
RXD0_3
RXD1_3
VDD
RXD3_1
RXD2_1
RXD1_1
RXD0_1
RXD
V_1
RXCLK_1
RXER_1/RXD4_1
TXER_1/TXD4_1
TXCLK_1
TXEN_1
TXD0_1
TXD1_1
TXD2_1
TXD3_1
GND
COL_1
CRS_1
GND
VDD
RXD3_2
RXD2_2
RXD1_2
RXD0_2
RXD
V_2
RXCLK_2
RXER_2/RXD4_2
TXER_2/TXD4_2
TXCLK_2
TXEN_2
TXD0_2
TXD1_2
TXD2_2
TXD3_2
COL_2
CRS_2
GND
VDD
RXD3_3
RXD2_3
GND
SD_THR
TPIP_0/FXOP_0
TPIN_0/FXON_0
SD_0/FXEN_0
TPOP_0/FXIN_0
VDD
GND
TPON_0/FXIP_0
VDD
GND
SD_1/FXEN_1
TPON_1/FXIP_1
VDD
GND
TPOP_1/FXIN_1
VDD
TPIN_1/FXON_1
TPIP_1/FXOP_1
GND
REXT
TPIP_2/FXOP_2
TPIN_2/FXON_2
SD_2/FXEN_2
TPOP_2/FXIN_2
VDD
GND
TPON_2/FXIP_2
VDD
GND
SD_3/FXEN_3
TPON_3/FXIP_3
VDD
GND
TPOP_3/FXIN_3
VDD
TPIN_3/FXON_3
TPIP_3/FXOP_3
GND
GND
4 of 118
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
April, 2002
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
1 Pin Description
Pin Description
Power Supplies
Pin #
Pin Name
I/O
Description
15
16
22
40
41
60
78
96
100
107
125
128
132
135
144
147
151
154
VDD
---
Positive Supply. +3.3 5%Volts.
7
14
21
39
56
59
77
95
108
121
122
127
131
134
141
146
150
153
160
GND
---
Ground. 0 Volts.
Pin Description
5 of 118
April, 2002
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
Media Interface
Pin #
Pin Name
I/O
Description
126
136
145
155
TPOP_[3:0]/
FXIN_[3:0]
I/O
Twisted Pair Transmit Output, Positive.
Fiber Receive Input, Negative.
129
133
148
152
TPON_[3:0]/
FXIP_[3:0]
I/O
Twisted Pair Transmit Output, Negative.
Fiber Receive Input, Positive.
123
139
142
158
TPIP_[3:0]/
FXOP_[3:0]
I/O
Twisted Pair Receive Input, Positive.
Fiber Transmit Output, Positive.
124
138
143
157
TPIN_[3:0]/
FXON_[3:0]
I/O
Twisted Pair Receive Input, Negative.
Fiber Transmit Output, Negative.
130
137
149
156
SD_[3:0]/
FXEN_[3:0]
I
Fiber Interface Signal Detect Input.
Fiber Interface Enable.
When this pin in not tied to GND, the fiber interface is enabled and
this pin becomes a Signal Detect ECL input. The trip point for this
ECL input is determined by the voltage applied to the SD_THR
pin. When this pin is tied to GND, the fiber interface is disabled
(i.e., TP Interface is enabled).
159
SD_THR
---
Fiber Interface Signal Detect Threshold Reference.
The voltage applied to this pin sets the reference level for the fiber
interface SD input pin so that the device can directly connect SD
pin to both 3.3V and 5V fiber optic transceivers. Typically, this pin
is either tied to GND (for 3.3V) or to an external voltage divider (for
5V).
140
REXT
---
Transmit Current Set.
An external resistor connected between this pin and GND will set
the level for the transmit outputs.
Pin Description (Cont.)
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