MD400182/B
April, 2002
1 of 88
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
L80225 10/100 MbpsTX/10BT
Ethernet Physical Layer Device
(PHY)
Technical Manual
Features
Note:
Check for the latest revision of this document before start-
ing any designs. This document is available on the Web, at
www.lsilogic.com
Single Chip 100Base-TX /10Base-T
physical layer solution
Dual Speed - 10/100 Mbps
Half and Full Duplex
MII interface to Ethernet Controller
MI interface for configuration & status
Optional Repeater Interface
AutoNegotiation: 10/100, Full/Half
Duplex
Meets all applicable IEEE 802.3
standards
Advertisement control through pins
Adaptive Equalizer
On-chip wave shaping - no external filters
required
Baseline Wander Correction
LED outputs
Link
Activity
Collision
Full Duplex
10/100
Few external components
3.3 V supply with 5 V tolerant I/O
44 PLCC
Contents
Description
- - - - - - - - - - - - - - - - - - - - - 2
Pin Description
- - - - - - - - - - - - - - - - - - 4
Block Diagram
- - - - - - - - - - - - - - - - - - - 8
Functional Description
- - - - - - - - - - - - - 9
Register Description
- - - - - - - - - - - - - - -43
Application Information
- - - - - - - - - - - - 51
Specifications
- - - - - - - - - - - - - - - - - - - 65
Ordering Information
- - - - - - - - - - - - - - 84
Revision History
- - - - - - - - - - - - - - - - - 84
Surface Mount Packages
- - - - - - - - - - - 87
2 of 88
L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
Description
The L80225 is a highly integrated analog interface IC for twisted pair
Ethernet applications. The L80225 can be configured for either
(100Base-TX) or 10 Mbps (10Base- T) Ethernet operation.
The L80225 consists of 4B5B/Manchester encoder/decoder,
scrambler/descrambler, transmitter with wave shaping and output driver,
twisted pair receiver with on chip equalizer and baseline wander
correction, clock and data recovery, AutoNegotiation, controller interface
(MII), and serial port (MI).
The addition of internal output waveshaping circuitry and on-chip filters
eliminates the need for external filters normally required in 100Base-TX
and 10Base-T applications.
The L80225 can automatically configure itself for 100 or 10 Mbps and
Full or Half Duplex operation with the on-chip AutoNegotiation algorithm.
The L80225 can access six 16-bit registers though the Management
Interface (MI) serial port. These registers contain configuration inputs,
status outputs, and device capabilities.
The L80225 is ideal as a media interface for 100Base-TX/ 10Base-T
adapter cards, motherboards, repeaters, switching hubs, and external
PHYs.
The L80225 operates from a single 3.3V supply. All inputs and outputs
are 5V tolerant and will directly interface to other 5V devices.
Description
3 of 88
April, 2002
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
Pin Configuration
FD_LED/(
MD
A1)
L_LED/(
MD
A0)
GND2
TPI-
TPI+
VDD1
TPO-
TPO+
DUPLX
GND1
ANEG
REXT
RESET
OSCIN
GND4
TX_EN
TX_ER
TXD3
TXD2
TXD1
TXD0
TX_CLK
C_LED/(MDA2)
LA_LED/(MDA3)
GND3
VDD2
SPEED
MDC
MDIO
COL
CRS
RX_DV
RX_ER
RXD3
RXD2
RXD1
RXD0
GND5
RPTR
VDD3
RX_CLK
RX_EN
GND6
VDD4
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
28
27
26
25
24
23
22
21
20
19
18
6
5
4
3
2
1
44
43
42
41
40
L80225
44 Pin PLCC
Top View
4 of 88
L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual
April, 2002
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
1 Pin Description
Pin Description
Pin #
Pin
Name
I/O
Description
28
24
10
1
VDD4
VDD3
VDD2
VDD1
--
Positive Supply. 3.3 V
5% Volts
27
22
36
9
4
41
GND6
GND5
GND4
GND3
GND2
GND1
--
Ground. 0 V
43
TPO+
O
Twisted Pair Transmit Output, Positive.
44
TPO -
O
Twisted Pair Transmit Output, Negative.
2
TPI+
I
Twisted Pair Receive Input, Positive.
3
TPI -
I
Twisted Pair Receive Input, Negative.
39
REXT
--
Transmit Current Set. An external resistor connected between this pin
and GND will set the output current for the TP and FX transmit outputs.
37
OSCIN
I
Clock Oscillator Input. There must be either a 25 MHz crystal between
this pin and GND or a 25 MHz clock applied to this pin. TX_CLK output
is generated from this input.
29
TX_CLK
O
Transmit Clock Output. This controller interface output provides a clock
to an external controller. Transmit data from the controller on TXD, TX_EN,
and TX_ER is clocked in on rising edges of TX_CLK and OSCIN.
35
TX_EN
I
Transmit Enable Input. This controller interface input has to be asserted
active high to indicate that data on TXD and TX_ER is valid, and it is
clocked in on rising edges of TX_CLK and OSCIN.
33
32
31
30
TXD3
TXD2
TXD1
TXD0
I
Transmit Data Input. These controller interface inputs contain input nibble
data to be transmitted on the TP outputs, and they are clocked in on rising
edges of TX_CLK and OSCIN when TX_EN is asserted.
34
TX_ER
I
Transmit Error Input. This controller interface input causes a special pat-
tern to be transmitted on the twisted pair outputs in place of normal data,
and it is clocked in on rising edges of TX_CLK when TX_EN is asserted.
Pin Description
5 of 88
April, 2002
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
25
RX_CLK
O
Receive Clock Output. This controller interface output provides a clock
to an external controller. Receive data on RXD, RX_DV, and RX_ER is
clocked out on falling edges of RX_CLK.
15
CRS
O
Carrier Sense Output. This controller interface output is asserted active
high when valid data is detected on the receive twisted pair inputs, and it
is clocked out on falling edges of RX_CLK.
16
RX_DV
O
Receive Data Valid Output. This controller interface output is asserted
active high when valid decoded data is present on the RXD outputs, and
it is clocked out on falling edges of RX_CLK.
18
19
20
21
RXD3
RXD2
RXD1
RXD0
O
Receive Data Output. These controller interface outputs contain receive
nibble data from the TP input, and they are clocked out on falling edges
of RX_CLK.
17
RX_ER
O
Receive Error Output. This controller interface output is asserted active
high when a coding or other specified errors are detected on the receive
twisted pair inputs and it is clocked out on falling edges of RX_CLK.
14
COL
O
Collision Output. This controller interface output is asserted active high
when a collision between transmit and receive data is detected.
12
MDC
I
Management Interface (MI) Clock Input. This MI clock shifts serial data
into and out of MDIO on rising edges.
13
MDIO
I/O
Management Interface (MI) Data Input/Output. This bidirectional pin
contains serial MI data that is clocked in and out on rising edges of the
MDC clock.
8
LA_LED/
(MDA3)
I/O
O.D.
Pullup
Link + Activity LED/Management Interface Address Input. This pin
indicates the occurrence of Link or Activity. It can drive an LED from VDD.
0 = Link Detect
Blink = Link Detect and Activity
1 = No Link Detect
During powerup or reset, this pin is high impedance and its value is
latched in as the physical device address MDA3 for the MI serial port.
7
C_LED/
(MDA2)
I/O
O.D.
Pullup
Collision LED Output/Management Interface Address Input. This pin
indicates the occurrence of a Collision. It can drive an LED from VDD.
0 = Collision Detect
1 = No Collision
During powerup or reset, this pin is high impedance and the value on this
pin is latched in as the physical device address MDA2 for the MI serial
port.
Pin Description (Cont.)
Pin #
Pin
Name
I/O
Description