ii
Copyright 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
DB14-000133-01, Second Edition (October 2002)
This document describes revision/release B of LSI Logic Corporation's
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY and will remain the official
reference source for all revisions/releases of this product until rescinded by an
update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI and the LSI Logic logo design are trademarks or registered trademarks of
LSI Logic Corporation. All other brand and product names may be trademarks of
their respective companies.
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
iii
Copyright 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the L80223
10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY). It
contains a complete functional description for the L80223 and includes
complete physical and electrical specifications for the product.
Audience
This document assumes that you have some familiarity with Ethernet
devices and related support devices. The people who benefit from this
book are:
Engineers and managers who are evaluating the device for possible
use in a system
Engineers who are designing the device into a system
Organization
This document has the following chapters:
Chapter 1, Introduction
, describes the device in general terms and
gives a block diagram and lists the device features.
Chapter 2, Functional Description
, describes each of the internal
blocks in the device in some detail.
Chapter 3, Signal Descriptions
, lists and describes the device input
and output signals.
Chapter 4, Registers
, gives a register summary and describes each
of the bits in each register.
Chapter 5, Management Interface
, describes the device
Management Interface, which allows the registers to be read and
written.
iv
Preface
Copyright 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chapter 6, Specifications
, lists the AC and DC characteristics and
gives typical timing parameters.
Appendix A, Application Information
, gives practical guidelines for
incorporating the device into a design.
Abbreviations Used in This Manual
Below is a list of abbreviations used throughout this manual.
100BASE-FX
100 Mbits/s Fiber Optic Ethernet
100BASE-T
100 Mbits/s Twisted-Pair Ethernet
10BASE-T
10 Mbits/s Twisted-Pair Ethernet
4B5B
4-Bit 5-Bit
CLK
Clock
CRC
Cyclic Redundancy Check
CRS
Carrier Sense
CSMA
Carrier Sense Multiple Access
CWRD
Codeword
DA
Destination Address
ECL
Emitter-Coupled Logic
EOF
End of Frame
ESD
End of Stream Delimiter
FCS
Frame Check Sequence
FDX
Full-Duplex
FEF
Far End Fault
FIFO
First In - First Out
FLP
Fast Link Pulse
HDX
Half-Duplex
HIZ
High Impedance
I/G
Individual/Group
IETF
Internet Engineering Task Force
IPG
Inter-Packet Gap
IREF
Reference Current
L/T
Length and Type
LSB
Least-Significant Bit
MIB
Management Information Base
MLT3
Multi-Level Transmission (3 levels)
ms
millisecond
MSB
Most-Significant Bit
mV
millivolt
NLP
Normal Link Pulse
NRZI
Non-Return to Zero Inverted
NRZ
Non-Return to Zero
OP
Opcode
PCB
Printed Circuit Board
pF
picofarad
Preface
v
Copyright 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix "0x" --for example,
0x32CF. Binary numbers are indicated by the prefix "0b" --for example,
0b0011.0010.1100.1111.
PRE
Preamble
R/LH
Read Latched High
R/LHI
Read Latched High with Interrupt
R/LL
Read Latched Low
R/LLI
Read Latched Low with Interrupt
R/LT
Read Latched Transition
R/LTI
Read Latched Transition with Interrupt
R/WSC
Read/Write Self Clearing
RFC
Request for Comments
RJ-45
Registered Jack-45
RMON
Remote Monitoring
SA
Start Address or Station Address
SFD
Start of Frame Delimiter
SNMP
Simple Network Management Protocol
SOI
Start of Idle
SSD
Start of Stream Delimiter
STP
Shielded Twisted Pair
TP
Twisted Pair
H
microhenry
P
microprocessor
UTP
Unshielded Twisted Pair
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