ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000032-03, April 2000
This document describes release B of LSI Logic Corporation's L64724 Satellite
Receiver and will remain the official reference source for all revisions/releases of
this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright 2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design and G10 are registered trademarks of LSI Logic
Corporation. All other brand and product names may be trademarks of their
respective companies.
L64724TM_300.book Page ii Friday, April 14, 2000 2:17 PM
Contents
iii
Contents
Chapter 1
Introduction
1.1
General Description
1-1
1.2
Typical Application
1-3
1.3
Features Summary
1-5
Chapter 2
L64724 Signal Definitions
2.1
Channel Interface
2-3
2.2
Channel Clock Interface
2-4
2.3
Phase-Locked Loop (PLL) Interface
2-4
2.4
Control Signals Interface
2-5
2.5
AGC/Clock Control Interface
2-6
2.6
Channel Data Output Interface
2-6
2.7
Analog-to-Digital Converter (ADC) Interface
2-7
2.8
Microcontroller Interfaceea
2-8
Chapter 3
L64724 Registers
3.1
L64724 Register Overview
3-1
3.2
Reset and How it Affects Registers
3-7
3.3
Groups 0 and 1: Address Pointer Register
3-8
3.4
Group 2: System Mode and System Status Registers
3-9
3.5
Group 3: Status Registers
3-23
3.6
Group 4: Configuration Registers
3-33
3.7
Group 5: Self-Tuning Microcontroller Registers
3-77
3.8
Group 6: Reserved (Internal Use Only)
3-81
3.9
Group 7: Arbiter Control Register
3-81
3.10
Reset Effect on Register Bits
3-82
3.11
Internal Data Path Reset Effects
3-84
L64724TM_300.book Page iii Friday, April 14, 2000 2:17 PM
iv
Contents
Chapter 4
Channel Interfaces and Data Control
4.1
Data Control and Clocking Schemes
4-2
4.2
PLL Clock Generation
4-3
4.3
Data Path Input Interface
4-12
4.4
Data Output Interface
4-14
Chapter 5
Demodulator Module Functional Description
5.1
Overview
5-2
5.2
Analog to Digital Conversion
5-2
5.3
DC Offset Compensation and Coupling to ADC Output
5-3
5.4
Decimation Filters
5-4
5.5
Matched Filter
5-7
5.6
Timing Clock Recovery
5-8
5.7
Carrier Recovery Loop
5-12
5.8
Automatic Gain Control (AGC)
5-20
5.9
Output Control
5-22
5.10
External Controls
5-23
Chapter 6
Decoding Pipeline Synchronization
6.1
Synchronization Scheme
6-1
6.2
Viterbi Decoder Synchronization
6-2
6.3
Reed-Solomon Deinterleaver Synchronization
6-8
6.4
Descrambler Synchronization
6-13
Chapter 7
The FEC Decoder Pipeline
7.1
Viterbi Decoder Module
7-1
7.2
Deinterleaver Module
7-8
7.3
Reed-Solomon Decoder
7-10
7.4
Descrambler Module Architecture and Operation
7-15
7.5
FEC Module Software Reset
7-17
Chapter 8
L64724 Specifications
8.1
Electrical Requirements
8-1
8.2
AC Timing
8-6
8.3
L64724 Packaging
8-15
L64724TM_300.book Page iv Friday, April 14, 2000 2:17 PM
Contents
v
Appendix A
Programming the L64724 Using the Serial Bus Protocol
A.1
Serial Bus Protocol Overview
A-2
A.2
Programming the Slave Address Using the Serial Bus
Interface
A-4
A.3
Write Cycle Using the Serial Bus Interface
A-4
A.4
Read Cycle Using the Serial Bus Interface
A-7
Appendix B
L64724 Application Notes
B.1
L64724 QPSK Demodulator Acquisition and Debugging
Tips
B-1
B.2
Demodulator Configuration Tips
B-5
B.3
QPSK Demodulator and FEC Configuration Example:
High Data Rates
B-10
B.4
QPSK Demodulator and FEC Configuration Example:
Low Data Rates
B-30
Appendix C
Programming the Serializer
C.1
Serializer Overview
C-1
C.2
Serializer Interface Signals and Configuration Registers
C-2
C.3
Programming for Serial Mode (2-Wire Compliant)
C-4
C.4
Programming for 3-Wire Mode
C-6
Appendix D
A/D Converters
D.1
ADC Overview
D-2
D.2
Board Level Interface
D-2
D.3
DC Characteristics
D-5
D.4
AC Characteristics
D-5
Appendix E
L64724 On-chip Microcontroller
E.1
L64724 Microcontroller Instruction Set
E-2
E.2
Microcontroller Address Map
E-5
Customer Feedback
L64724TM_300.book Page v Friday, April 14, 2000 2:17 PM
PDF 
ZIP