September 1999
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Copyright 1998, 1999 by LSI Logic Corporation. All rights reserved.
The TinyRISCTM EZ4102 EasyMACRO subsystem is a compact, high-
performance, 32-bit MIPS microprocessor subsystem implemented in LSI
Logic's G11TM technology. The EZ4102 combines the TinyRISC CPU
with the most commonly used blocks (such as a bus controller, MMU,
and EJTAG) to simplify system-on-a-chip design and reduce time to
market. A bus controller module (FBusMACRO) and RAMs are also
available from LSI Logic to help speed your CoreWare
design.
The EZ4102 is appropriate for any embedded application that demands
low power with code compression, and can be easily designed into a
wide range of products. Figure 1 shows the EZ4102 and how it interfaces
with system logic in a typical design.
Figure 1
EZ4102 in a Typical System
The EZ4102 is powered by either 2.5 V or 1.8 V. For 2.5 V operation, the
EZ4102 is rated at 85 MHz (worst case conditions) with a performance
of 85 MIPS peak and 68 MIPS sustainable. For 1.8 V operation, the
EZ4102 is rated at 50 MHz (worst case conditions) with a performance
of 50 MIPS peak and 40 MIPS sustainable. The EZ4102 utilizes G11
32-bit TinyRISC
EZ4102 EasyMACRO Subsystem
Two 32-bit Timers
UART
EJTAG
FlexLink
CBus
Caches and Tags
BBus
EJTAG Interface
SerialICETM-1 Interface
MMU
EJTAG Extended Debug MACRO (PC Trace)
BIU and Cache
4102 CPU
and
FastMDU
Controller (BBCC)
TLB RAM
PC Trace Output
FBus
Clock
Controller
FBusMACRO
TinyRISCTM EZ4102
EasyMACRO Microprocessor
Preliminary Datasheet
2
TinyRISC EZ4102 EasyMACRO Microprocessor
technology and implements a full-scan methodology to achieve very high
fault coverage.
EZ4102 Overview and Features
Components
MIPS R3000 CPU, executing MIPS I,
MIPS II, and MIPS16 instructions
EJTAG Interface and Controller
Nonintrusive debug
Real-time PC trace (requires
Extended Debug MACRO)
Hardware breakpoints (requires
Extended Debug MACRO)
FastMDU
5 cycle 32-bit to 64-bit multiply and
accumulate
34/35 cycle divide
Basic BIU and Cache Controller
(BBCC) with four write back buffers
included
Two 32-bit Timers
MMU supports a 64-entry TLB RAM
ICEport included for backward
compatibility with SerialICE-1 debugger
Caches:
1 to 32 Kbytes of direct-mapped or
set-associative I-Cache
1 to 32 Kbytes of direct-mapped
D-Cache
Technology
LSI Logic's G11TM Technology with
0.18-
L
eff
(0.25-
L
drawn
)
2.5 or 1.8 V operation
Features
All configuration through EasyMACRO
interfaces, no external logic needed
Clock speed is 85 MHz at 2.5 V
(85 MIPS peak and estimated 68 MIPS
sustainable)
16-bit and 32-bit code can be mixed
arbitrarily with full support on a
subroutine basis
Optional FBusMACRO (controller)
available from LSI Logic to speed
system development
Models available: performance and
software development, VHDL, Verilog,
and gate level, timing-accurate models
Compatible with the full range of MIPS,
third-party software development, and
system verification environment tools
Implementation of full-scan methodology
to achieve very high design fault
coverage
TinyRISC EZ4102 EasyMACRO Microprocessor
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EZ4102 Design Support
The EZ4102 EasyMACRO subsystem has all the necessary tools to
develop a system on a chip, including:
LSI Logic TinySIMTM architectural simulator
Verilog and VHDL models
System verification environment
EJTAG on-chip debugger
Third-party software support
LR4102 microprocessor chip and evaluation kit for evaluation and
prototyping
The EZ4102 supports the LSI Logic EJTAG interface, which enables
software development and hardware design debugging from a remote
host. EJTAG uses the EZ4102 EJTAG pins to provide a debug solution
with breakpoint capability and real-time trace of the program counter
(requires Extended Debug MACRO). A SerialICE-1 ICEport has also
been added to the EZ4102 for backward compatibility with any existing
TinyRISC designs.
The CoreWare program consists of three main elements:
1.
A library of cores
2.
A design development and simulation package
3.
Expert applications support
The CoreWare library contains a wide range of complex cores based on
accepted and emerging industry standards from high-speed interconnect
and digital video to DSP and MIPS microprocessors. LSI Logic provides
a complete framework for device and system development and
simulation. LSI Logic has advanced ASIC technologies that consistently
produce Right-First-TimeTM silicon. LSI Logic's in-house experts provide
design support from system architecture definition through chip layout
and test vector generation.
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TinyRISC EZ4102 EasyMACRO Microprocessor
Block Diagram
Figure 2 is a block diagram of the TinyRISC EZ4102 EasyMACRO
Microprocessor. Descriptions of the internal EZ4102 components follow
the figure.
Figure 2
EZ4102 EasyMACRO Block Diagram
The TR4102 CPU performs all arithmetic, logical, shift, and address
calculations. The CPU supports EJTAG debug and is closely coupled
with the FastMDU. The FastMDU calculates all multiply and divide
operations for the EZ4102 and provides 5 cycle 32 x 32 = 64 bit multiply
and accumulate operations, 34/35 cycle divide, saturated math, and
overflow indication.
The Basic BIU and Cache Controller (BBCC) controls the
internal/external BBus arbitration and connects the EasyMACRO
subsystem to the caches. Four Write Buffers are integrated with the
BBCC in the EZ4102. The BBus connects the BBCC, the SerialICE-1
and EJTAG units, and the two internal timers with logic implemented
inside the EZ4102.
The optional 32-bit FBusMACRO controls the FBus, a dedicated,
multimaster bus that connects outside devices with the EZ4102 internal
32-bit TinyRISC
EZ4102 EasyMACRO Subsystem
32-Bit Timers
UART
EJTAG
FlexLink
CBus
Caches and Tags
BBus
EJTAG Interface
SerialICE-1 Interface
MMU
EJTAG Extended Debug MACRO (PC Trace)
Basic BIU and Cache
TR4102 CPU
and
FastMDU
Controller (BBCC)
FBusMACRO
TLB RAM
TinyRISC EZ4102 EasyMACRO Microprocessor
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components. The optional FBus controller allows seamless connection to
a variety of devices, including EPROM, RAM, DRAM, SDRAM, and
general purpose I/Os. The FBus also supports burst read (one cycle) and
write, built-in arbitration for external FBus masters, and snooping of
external write accesses to memory. The FBus connects to the BBus.
The Memory Management Unit (MMU) controls the Translation
Look-Aside Buffer (TLB) RAM.
The two internal 32-bit Timers are controlled by the CPU. Each timer can
count down from a preloaded value, roll over or stop at zero, or generate
an interrupt on zero. The timers can also be used as a BBus Watchdog
Timer to monitor BBus transactions.
The EJTAG Interface provides an on-chip debug scheme with breakpoint
capability in an EJTAG compatible design. The EJTAG debugger
provides real-time PC trace and hardware breakpoint capabilities
(requires Extended Debug MACRO).
A SerialICE-1 Interface (UART) is also included in the EasyMACRO
subsystem to promote backward compatibility with an existing TinyRISC
design.
The CBus Interface passes data to and from the CPU. This interface
connects the CPU to the MMU, the BBCC, and up to three optional
coprocessors and on-chip memory implemented outside the
EasyMACRO subsystem.
The FlexLink Interface allows the logic designer to insert specialized
arithmetic instructions into the microprocessor EasyMACRO subsystem.
The FlexLink interface can handle one-cycle and multicycle operations.
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