ii
Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
This document is preliminary. As such, it contains data derived from functional
simulations and performance estimates. LSI Logic has not verified either the
functional descriptions, or the electrical and mechanical specifications using
production parts.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000127-00, First Edition (March 2000)
This document describes LSI Logic Corporation's ARM7TDMI-S Microprocessor
Core and will remain the official reference source for all revisions/releases of this
product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright 2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic logo design, CoreWare and CoreWare logo design, GigaBlaze, G10
and G10 logo design, G11 and G11 logo design, G12 and G12 logo design,
Right-First-Time are trademarks or registered trademarks of LSI Logic
Corporation. ARM is a registered trademark of Advanced RISC Machines
Limited, used under license. All other brand and product names may be
trademarks of their respective companies.
EH
Preface
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Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the
ARM7TDMI-S core. It contains a complete functional description and
complete electrical specifications for the ARM7TDMI-S core.
Audience
This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are:
Engineers and managers who are evaluating the processor for
possible use in a system
Engineers who are designing the processor into a system
Organization
This document has the following chapters and appendixes:
Chapter 1, Introduction
, introduces the ARM7TDMI-S core and
summarizes the LSI Logic CoreWare program.
Chapter 2, Signal Descriptions
, describes the signals that make up
the external interface of the ARM7TDMI-S core.
Chapter 3, Programmer's Model
, describes the operating states
and registers of the ARM7TDMI-S core.
Chapter 4, Memory Interface
, provides details on the ARM7TDMI-S
memory interface.
Chapter 5, Coprocessor Interface
, describes the ARM7TDMI-S
coprocessor interface.
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Preface
Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
Chapter 6, Debug Interface
, describes the ARM7TDMI-S debug
interface.
Chapter 7, Instruction Cycle Timing
, provides the instruction cycle
timing for the ARM7TDMI-S core.
Appendix A, Differences Between the ARM7TDMI-S and the
ARM7TDMI
, describes the differences between the ARM7TDMI-S
and the ARM7TDMI hard macrocell.
Appendix B, Detailed Debug Operation
, provides extensive detail of
the debug operation of the ARM7TDMI-S core.
Related Publications
ARM7TDMI Microprocessor Core Technical Manual, Document No.
DB14-000058-02
ARM Architecture Reference Manual (ARM DDI 0100).
ARM7TDMI Data Sheet (ARM DDI 0029).
IEEE Std. 1149.1- 1990,
Standard Test Access Port and Boundary-Scan
Architecture.
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is
italicized.
The word
assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW contain a lowercase "n."
Hexadecimal numbers are indicated by the prefix "0x" --for example,
0x32CF. Binary numbers are indicated by the prefix "0b" --for example,
0b0011.0010.1100.1111.
Contents
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Rev. A
Copyright 2000 by LSI Logic Corporation. All rights reserved.
Contents
Preface
Chapter 1
Introduction
1.1
Introduction
1-1
1.1.1
General Information
1-1
1.1.2
LSI Logic's ARM7TDMI-S Implementation
1-2
1.2
ARM7TDMI-S Architecture
1-2
1.2.1
Instruction Compression
1-2
1.2.2
The Thumb Instruction Set
1-3
1.2.3
Pipeline Architecture
1-5
1.2.4
Memory Accesses
1-6
1.2.5
Memory Interface
1-7
1.3
ARM7TDMI-S Core Instruction Set Summary
1-7
1.3.1
ARM Instruction Summary
1-9
1.3.2
Thumb Instruction Summary
1-18
1.4
CoreWare
Program
1-23
Chapter 2
Signal Descriptions
2.1
Memory Interface
2-3
2.2
Coprocessor Interface
2-6
2.3
Clock and Control Signals
2-7
2.4
Debug Interface
2-9
2.5
ATPG Interface
2-11
Chapter 3
Programmer's Model
3.1
Processor Operating States
3-1
3.2
Memory Formats
3-2
3.2.1
Big-Endian Format
3-2
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