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Электронный компонент: LS7266R1

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24-BIT DUAL-AXIS QUADRATURE COUNTER
LS7266R1 Registers:
LS7266R1 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X,
whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode
of the three most significant bits (D7-D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects
between control and data information for Read/Write. Following is a complete list of LS7266R1 registers.
December 2002
7266R1-121002-1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
YLCNTR/YLOL
FCK
V
DD
(+5V)
D0
D1
D2
D3
D4
D5
D6
D7
V
SS
(GND)
C/D
WR
LS7266R1
CS
RD
XRCNTR/XABG
XLCNTR/XLOL
XA
XB
XFLG1
YA
YB
YFLG2
YFLG1
YRCNTR/YABG
XFLG2
X/Y
PIN ASSIGNMENT - TOP VIEW
28-Pin Package
Preset Registers: XPR and YPR
Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data
write cycles.
7
7
0
0 7
0
HI BYTE
MID BYTE
LO BYTE
PR
( P R 2 )
( P R 1 )
( P R 0 )
Output Latches: XOL and YOL
Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded
into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read
cycles.
7
7
0
0 7
0
HI BYTE
MID BYTE
LO BYTE
OL
( O L 2 )
( O L 1 )
( O L 0 )
Counters: XCNTR and YCNTR
Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its
associated A/B inputs. Each CNTR can be loaded with the content of its associated PR.
Byte Pointers: XBP and YBP
The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is
addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is
automatically incremented to address the next byte.
FEATURES:
30 MHz count frequency in non-quadrature mode,
17MHz in x4 quadrature mode.
Dual 24-bit counters to support X and Y axes in
motion control applications.
Dual 24-bit comparators.
Digital filtering of the input quadrature clocks
Programmable 8-bit separate filter clock prescalers
for each axis.
Error flags for noise exceeding filter band width.
Programmable Index Input and other programmable I/Os.
Independent mode programmability for each axis.
Programmable count modes:
Quadrature (x1, x2, x4) / Non-quadrature,
Normal / Modulo-N / Range Limit / Non-Recycle,
Binary / BCD.
8-bit 3-State data I/O bus.
5V operation (V
DD
-V
SS
).
TTL/CMOS compatible I/Os.
LS7266R1 (DIP); LS7266R1-SD (Skinny DIP);
LS7266R1-S (SOIC); LS7266R1-TS (TSSOP)
LSI/CSI
LS7266R1
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
UL
A3800
7
6
5
4
3
2
1
0
BT: Borrow Toggle flip-flop.
Toggles every time CNTR underflows.
CT: Carry toggle flip-flop.
Toggles every time CNTR overflows.
CPT: Compare toggle flip-flop.
Toggles every time PR equals CNTR.
S: Sign flag. Set to1 when CNTR underflows.
Reset to 0 when CNTR overflows.
FLAG
E: Error flag. Set to 1 when excessive noise is present at the count
inputs in quadrature mode. Irrelevant in non-quadrature mode.
U/D: Up/Down flag. Set to 1 when counting up
and reset to 0 when counting down.
Not used. Always reset to 0.
IDX: Index. Set to 1 when selected index input is at active level.
0
Filter Clock Prescalers: XPSC and YPSC
Each PSC is an 8-bit programmable modulo-N down counter, driven by the FCK clock. The factor N is down loaded
into a PSC from the associated PR low byte register PR0. The PSCs provide the ability to generate independent filter
clock frequencies for each channel. The PSCs generate the internal filter clock, FCKn used to
validate inputs X
A
, X
B
, Y
A
, Y
B
in the quadrature mode.
Final filter clock frequency f
FCKn
= ( f
FCK
/(n+1) )
,
where n = PSC = 0 to FF
H.
For proper counting in the quadrature
mode, f
FCK
n
8f
QA
(or 8f
QB
), where f
QA
and f
QB
are the clock frequencies at inputs A and B. In non-quadrature mode
filter clock is not needed and the FCK input (Pin 2), should be tied to V
DD
.
7266R1-111196-2
Flag Register: XFLAG and YFLAG
The FLAG registers hold the status information of the CNTRs and can be read out on the data bus. The E bit of a
FLAG register is set to 1 when the noise pulses at the quadrature inputs are wide enough to be validated by the
input filter circuits. E = 1 indicates excessive noise at the inputs but not a definite count error. Once set, E can
only be reset via the RLD.
7
6
5
4
3
2
1
0
0: NOP
0
1
0
RLD
1: Reset BP
0
0
1
0
1
1
0
0 : Select the RLD addressed by X/Y input
1 : Select both XRLD and YRLD together
(Note: D7 = 1 overrides X/Y input)
: Select RLD
: NOP
: Reset CNTR
: Reset BT, CT, CPT,S
: Reset E
0
0
1
0
0
1
1
1
: NOP
: Transfer PR to CNTR
(Note: All 24-bits are transferred in parallel)
: Transfer CNTR to OL
(Note: All 24-bits are transferred in parallel)
: Transfer PR0 to PSC
Reset and Load Signal Decoders: XRLD and YRLD
Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer
CNTR to OL, reset CNTR, reset FLAG and reset BP
.
:
7266R1-111196-3
Counter Mode Registers: XCMR and YCMR
The CNTR operational mode is programmed by writing into the CMRs.
7
6
5
4
3
2
1
0
0 : Binary count
: Normal count
: Range Limit
: Non-recycle count
: Modulo-N
CMR
1 : BCD count
0
0
1
1
: Quadrature X1
0
: Non-quadrature
: Quadrature X2
1
: Quadrature X4
1
0: Select CMR addressed by X/Y input
1: Select both XCMR and YCMR together (Note: D7=1 overrides X/Y input)
: Select CMR
0
0
1
0
1
1
0
1
1
0
0
DEFINITIONS OF COUNT MODES:
Range Limit. In range limit count mode, an upper and a lower limit is set, mimicking limit switches in the me-
chanical counterpart. The upper limit is set by the content of the PR and the lower limit is set to be 0. The
CNTR freezes at CNTR = PR when counting up and at CNTR=0 when counting down. At either of these limits,
the counting is resumed only when the count direction is reversed.
Non-Recycle. In non-recycle count mode, the CNTR is disabled, whenever a count overflow or underflow takes
place. The end of cycle is marked by the generation of a Carry (in Up Count) or a Borrow (in Down Count). The
CNTR is re-enabled when a reset or load operation is performed on the CNTR.
Modulo-N. In modulo-N count mode, a count boundary is set between 0 and the content of PR. When counting
up, at CNTR=PR, the CNTR is reset to 0 and the up count is continued from that point. When counting down, at
CNTR=0, the CNTR is loaded with the content of PR and down count is continued from that point.
The modulo-N is true bidirectional in that the divide-by-N output frequency is generated in both up and down di-
rection of counting for same N and does not require the complement of N in the UP instance. In frequency di-
vider application, the modulo-N output frequency can be obtained at either the Compare (FLG1) or the Borrow
(FLG2) output. Modulo-N output frequency, f
N
= (f
i
/ (N+ 1) ) where f
i
= Input count frequency and N = PR.
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
Input/Output Control Register: XIOR and YIOR
The functional modes of the programmable input and output pins are written into the IORs.
7
6
5
4
3
2
1
0
0 : Disable inputs A and B
0 : LCNTR/LOL pin is Load CNTR input
0 : RCNTR/ABG pin is Reset CNTR input
0
IOR
1 : Enable inputs A and B
1 : LCNTR/LOL pin is Load OL input
1 : RCNTR/ABG pin is A and B Enable gate
0
0
: FLG1 pin is COMPARE output; FLG2 pin is BORROW output
1
: FLG1 pin is CARRY output; FLG2 pin is BORROW output
: FLG1 pin is Carry/Borrow output and FLG2 pin is U/D (FLAG register bit 5)
: FLG1 is IDX (FLAG register bit 6); FLG2 is E (FLAG register bit 4)
0: Select IOR addressed by X/Y input
1: Select both XIOR and YIOR together (Note: D7=1 overrides X/Y input)
: Select IOR
1
1
1
0
1
0
7266R1-120899-4
INDEX CONTROL REGISTERS: XIDR and YIDR
Either the LCNTR/LOL or the RCNTR/ABG inputs can be initialized to operate as an index input. When
initialized as such, the index signal from the encoder, applied to one of these inputs performs either the
Reset CNTR or the Load CNTR or the Load OL operation synchronously with the quadrature clocks. Note
that only one of these inputs can be selected as the Index input at a time and hence only one type of in-
dexing function can be performed in any given set-up.
The index function must be disabled in non-quadrature count mode.
7
6
5
4
3
2
1
0
0: Disable Index
0: Negative Index Polarity
0: LCNTR/LOL pin is indexed (See Note 1)
IDR
1: Enable Index
1: Positive Index Polarity
1: RCNTR/ABG pin is indexed (See Note 2)
1
1
0: Select IDR addressed by X/Y input
Not used
: Select IDR
1: Select both XIDR and YIDR (Note: D7=1 overrides X/Y input)
Note 1: Function selected for this pin via IOR, becomes the operating INDEX function.
Note 2: RCNTR/ABG input must also be initialized as the reset CNTR input via IOR
:
(See Note 3)
Note 3:
"Enable Index" causes the synchronous mode for the selected index input (as described in Pin 18
and Pin 19 sections of the I/O Description) to be enabled. "Disable Index" causes the
non-synchronous mode to be enabled. The input, however, is not disabled in either selection.
(See Note 3)
Absolute Maximum Ratings:
Parameter Symbol Values Unit
Voltage at any input
V
IN
V
SS
- 0.3 to V
DD
+ 0.3
V
Supply Voltage
V
DD
+7.0
V
Operating Temperature
T
A
-25 to +80
oC
Storage Temperature
T
STG
-65 to +150
oC
DC Electrical Characteristics. (T
A
= -25
C to +80
C, V
DD
= 4.5V to 5.5V)
Parameter Symbol Min. Value Max.Value Unit Remarks
Supply Voltage
V
DD
4.5
5.5
V
-
Supply Current
I
DD
-
800
A
All clocks off
Input Logic Low
V
IL
-
0.8
V
-
Input Logic High
V
IH
2.0
-
V
-
Output Low Voltage
V
OL
-
0.5
V
I
OSNK
= 5mA
Output High Voltage
V
OH
V
DD
- 0.5
-
V
I
OSRC
= 1mA
Input Leakage Current
I
ILK
-
30
nA
-
Data Bus Leakage Current
I
DLK
-
60
nA
Data bus off
Output Source Current
I
OSRC
1.0
-
mA
V
O
= V
DD
- 0.5V
Output Sink Current
I
OSNK
5.0
-
mA
V
O
= 0.5V
7266R1-111196-5
REGISTER ADDRESSING MODES
D7
D6
D5
C/D
RD
WR
CS
FUNCTION
X
X
X
X
X
1
Disable both axes for Read/Write
X
X
0
1
0
X
X
0
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
Write to XPR byte segment addressed by XBP (Note 3)
Write to YPR byte segment addressed by YBP (Note 3)
Write to XRLD
Write to both XRLD and YRLD
Write to XCMR
X
X
X
0
0
1
0
X/Y
X
0
1
0
1
X
0
0
0
1
1
1
0
1
0
1
1
1
1
0
X
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
1
X
0
Write to YRLD
Write to YCMR
Write to both XCMR and YCMR
Write to XIOR
Write to YIOR
Write to both XIOR and YIOR
X = Don't Care
Note 3 : Relevant BP is automatically incremented at the trailing edge of RD or WR pulse
1
1
1
1
X
X
X
0
0
0
0
X
X
X
0
0
1
0
X
X
X
1
0
0
0
X
X
X
1
0
1
0
Read XOL byte segment addressed by XBP (Note 3)
Read YOL byte segment addressed by YBP (Note 3)
Read XFLAG
Read YFLAG
1
1
1
1
0
Write to XIDR
0
0
0
1
1
1
1
0
1
1
1
1
1
1
0
X
Write to YIDR
Write to both XIDR and YIDR
7266R1-011498-6
Transient Characteristics. (T
A
= -25C to +80C, V
DD
= 4.5V to 5.5V)
Parameter Symbol Min. Value Max.Value Unit Remarks
Read Cycle
(See Fig. 1)
RD Pulse Width
t
r1
50
-
ns
-
CS Set-up Time
t
r2
50
-
ns
-
CS Hold Time
t
r3
0
-
ns
-
C/D Set-up Time
t
r4
50
-
ns
-
C/D Hold Time
t
r5
10
-
ns
-
X/Y Set-up Time
t
r6
50
-
ns
-
X/Y Hold Time
t
r7
10
-
ns
-
Data Bus Access Time
t
r8
50
-
ns
Access starts when both RD
and CS are low.
Data Bus Release Time
t
r9
-
25
ns
Release starts when either RD
or CS is terminated.
Back to Back Read delay
t
r10
60
-
ns
-
Write Cycle (See Fig. 2)
WR Pulse Width
t
W1
30
-
ns
-
CS Set-up Time
t
W2
30
-
ns
-
CS Hold Time
t
W3
0
-
ns
-
C/D Set-up Time
t
W4
30
-
ns
-
C/D Hold Time
t
W5
10
-
ns
-
X/Y Set-up Time
t
W6
30
-
ns
-
X/Y Hold Time
t
W7
10
-
ns
-
Data Bus Set-up Time
t
W8
30
-
ns
-
Data Bus Hold Time
t
W9
10
-
ns
-
Back to Back Write Delay
t
W10
60
-
ns
-
Quadrature Mode (See Fig. 3-5)
FCK High Pulse Width
t
1
14
-
ns
-
FCK Low Pulse Width
t
2
14
-
ns
-
FCK Frequency
f
FCK
-
35
MHz
-
Mod-n Filter Clock(FCKn)Period
t
3
28
-
ns
t
3
= (n+1) (t
1
+t
2
), where
n = PSC = 0 to FF
H
FCKn frequency
f
FCKn
-
35
MHz
-
Quadrature Separation
t
4
57
-
ns
t
4
2t
3
Quadrature Clock Pulse Width
t
5
115
-
ns
t
5
4t
3
Quadrature Clock frequency
f
QA
,
f
QB
-
4.3
MHz
f
QA
= f
QB
= 1/8t
3
Quadrature Clock to Count Delay
t
Q1
5t
3
6t
3
-
-
X1/X2/X4 Count Clock Pulse Width t
Q2
28
-
ns
t
Q2
= t
3
Index Input Pulse Width
t
idx
85
-
ns
t
idx
3t
3
Index Skew from A
t
Ai
-
28
ns
t
Ai
t
3
Carry/Borrow/Compare Output Width
t
Q3
28
-
ns
t
Q3
= t
3
Non-Quadrature Mode (See Fig. 6-7)
Clock A - High Pulse Width
t
6
16
-
ns
-
Clock A - Low Pulse Width
t
7
16
-
ns
-
Direction Input B Set-up Time
t
8S
20
-
ns
-
Direction Input B Hold Time
t
8H
20
-
ns
-
Gate Input (ABG) Set-up Time
t
GS
20
-
ns
-
Gate Input (ABG) Hold Time
t
GH
20
-
ns
-
Clock Frequency (non-Mod-N)
f
A
-
30
MHz
f
A
= (1/ (t
6
+ t
7
) )
Clock Frequency (Mod-N)
f
AN
-
25
MHz
-
Clock to Carry or Borrow Out Delay
t
9
-
30
ns
-
Carry or Borrow Out Pulse Width
t
10
16
-
ns
t
10
= t
7
Load CNTR, Reset CNTR and
Load OL Pulse Width
t
11
20
-
ns
-
Clock to Compare Out Delay
t
12
50
-
ns
-
INPUTS/OUTPUTS
X-AXIS I/Os:
XA (Pin 20)
X-axis count input A
XB (Pin 21)
X-axis count input B
XLCNTR/XLOL
X-axis programmable input, to operate as either direct load XCNTR or direct load XOL or synchronous
(Pin 19)
load XCNTR or synchronous load XOL. The synchronous load mode is intended for interfacing with
the encoder Index output in quadrature clock mode. In direct load mode, a logic low level is the active
level at this input. In synchronous load mode the active level can be programmed to be either logic
low or logic high. Both quarter-cycle and half-cycle Index signals are supported by this input in the in-
dexed Load mode. The synchronous function must be disabled in non-quadrature count mode (See
description of IDR on P. 4)
XRCNTR/XABG
X-axis programmable input to operate either as direct reset XCNTR or count enable/disable gate or
(Pin 18)
synchronous reset XCNTR. The synchronous reset XCNTR mode is intended for interfacing with the
encoder Index output in quadrature clock mode. In direct reset XCNTR mode, a logic low level is the
active level at this input whereas in synchronous reset XCNTR mode the active level can be pro-
grammed to be either a logic low or a logic high. Both quarter-cycle and half-cycle index signals are
supported by this input in the indexed reset CNTR mode. The synchronous function must be disabled
in non-quadrature count mode (See description of IDR on P. 4). In count enable/disable mode, a logic
high at this input enables the counter and a logic low level disables the counter.
XFLG1 (Pin 22)
X-axis programmable output to operate either as XCARRY (Active low), or XCOMPARE (generated
when XPR=XCNTR; Active low), or XIDX (XFLAG bit 6) or XCARRY/XBORROW (Active low).
XFLG2 (Pin 23)
X-axis programmable output to operate as either XBORROW (Active low) or XU/D (XFLAG bit 5)
or XE (XFLAG bit 4).
Y-AXIS I/Os:
All the X-axis inputs/outputs are duplicated for the Y-axis with similar functionalities.
YA (Pin 25)
YB (Pin 24)
YLCNTR/YLOL (Pin 1)
YRCNTR/YABG (Pin 28)
YFLG1 (Pin 27)
YFLG2 (Pin 26)
COMMON I/Os:
WR (Pin 14)
Write input. Control/data bytes are written at the trailing edge of low level pulse applied to this input.
RD (Pin 16)
Read input. A low level applied to this input enables the FLAGs and OLs to be read on the data bus.
CS (Pin 15)
Chip select input. A low level applied to this input enables the chip for Read and Write.
C/D (Pin 13)
Control/Data input. This input selects between a control register or a data register for Read/Write.
When low, a data register is selected. When high, a control register is selected.
D0-D7
Data Bus input/output. The 8-bit three-state data bus is the I/O port through which all data transfers
(Pins 4-11)
take place between the LS7266R1 and the host processor.
FCK (Pin 2)
Filter clock input in quadrature mode. The FCK is divided down internally by two 8-bit programmable
prescalers, one for each channel.
X/Y (Pin 17)
Selects between X and Y axes for Read or Write. X/Y = 0 selects X-axis and X/Y = 1 selects Y-axis.
X/Y is overridden by D7 =1 in Control Write Mode (C/D = 1).
V
DD
(Pin 3)
+5VDC
V
SS
(Pin 12)
GND
Either quadrature encoded clocks or non-quadrature clocks can be applied
to XA and XB. In quadrature mode XA and XB are digitally filtered and decoded
for UP/DN clock. In non-quadrature mode, the filter and the decoder circuits are
by-passed. Also, in non-quadrature mode XA serves as the count input and XB
as the UP/DOWN direction control input, with XB = 1 selecting Up Count mode
and XB = 0, selecting Down Count mode.
7266R1-011498-7
7266R1-111196-8
RD
CS
C/D
X/Y
DB
VALID
DATA
VALID DATA
tr
1
tr
10
tr
2
tr
3
tr
4
tr
5
tr
6
tr
7
tr
8
tr
9
FIGURE 1. READ CYCLE
tw
5
tw
7
tw
9
tw
3
tw
2
tw
4
tw
6
tw
8
INPUT DATA
tw
1
tw
10
INPUT DATA
WR
CS
C/D
X/Y
DB
FIGURE 2. WRITE CYCLE
t
1
t
2
t
3
t
5
t
4
t
4
t
4
t4
t
5
FIGURE 3. FILTER CLOCK FCK AND QUADRATURE CLOCKS A AND B
FCK
FCK
n
(Note 4)
A
B
Note 4: FCK
n
is the final modulo-n internal filter clock, arbitrarily shown here as modulo-1.
Note 5: Shown here is positive index with solid line depicting 1/4 cycle index and dotted line depicting 1/2 cycle index.
Either LCNTR/LOL or RCNTR/ABG input can be used as the INDEX input.
UP
DOWN
t
Ai
t
idx
A
B
INDEXI
(Note 5)
X1 CLOCK
(Note 6)
X4 CLOCK
(Note 6)
IDX
(Note 7)
FIGURE 4. QUADRATURE CLOCK A, B AND INDEX INPUT
Note 6: X1, X2 and X4 clocks are the final internal Up/Down count clocks derived
from filtered and decoded Quadrature Clock inputs, A and B.
Note 7: IDX is the synchronized internal "load OL" or "load CNTR" or "reset CNTR" signal based on LCNTR/LOL
or RCNTR/ABG input being selected as the INDEX input, respectively. This signal is identical with
FLAG register bit 6.
t
Q1
t
Q2
X2 CLOCK
(Note 6)
t
Ai
7266R1-062896-9
A
B
X4 CLOCK
(Internal)
CNTR
CY
BW
COMPARE
(Note 8)
CT(FLAG-B1)
BT(FLAG-B0)
CPT(FLAG-B2)
FIGURE 5. CARRY, BORROW, COMPARE, CARRY TOGGLE, BORROW TOGGLE AND
COMPARE TOGGLE IN X4 QUADRATURE, NORMAL, BINARY COUNT MODE.
Note 8: COMPARE is generated when PR = CNTR. In this timing diagram it is arbitrarily assumed that PR = 1.
t
Q3
t
Q2
t
t
Q3
FFFFFD FFFFFE FFFFFF
FFFFFF FFFFFE
0
1
2
3
2
1
0
UP
DOWN
t
Q3
t
8H
t
GS
t
GH
DOWN
UP
DOWN
t
8S
FIGURE 6. COUNT (A), DIRECTION (B) AND GATE (ABG) INPUTS IN NON-QUADRATURE MODE
COUNT DISABLE
COUNT ENABLE
DIRECTION (B)
COUNT IN (A)
GATE (ABG)
7266R1-011498-10
A
B
CNTR
RCNTR
BW
CNTR DISABLED
t
9
CNTR ENABLED
CNTR DISABLED
CNTR ENABLED
t
11
CNTR ENABLED
t
11
CNTR DISABLED
t
10
CY
LCNTR
FIGURE 7. NON-RECYCLE, NON-QUADRATURE, BCD MODE
999998 999999
999999
0
1
2
1
0
0
N
N-1
N-2
999999
t
9
A
B
CNTR
COMP
BW
0
1
2
3
0
1
2
1
0
3
2
1
2
3
0
UP
DOWN
FIGURE 8. MODULO - N, NON-QUADRATURE
(Shown with N = 3)
t
12
A
B
CNTR
COMP
BW
UP
DOWN
0
1
2
3
4 (CNTR FROZEN)
3
2
1
0 (CNTR FROZEN)
1
2
FIGURE 9. RANGE LIMIT, NON-QUADRATURE
(Shown with PR = 4)
UP
WRITE
INPUT REG
FLAG (8)
BP
RLD
CMR
IOR
IDR
PR2
PR1
PR0
CNTR
COMPARATOR
BYTE 0
BYTE 1
BYTE 2
I/O BUF
DATA-BUS
READ/WRITE
OL2
OL1
OL0
SBYTE2
SBYTE1
SBYTE0
DIRECTION
COUNT CLOCK
ERROR
CLOCK
GEN/FILTER
FCK PRESCALER
PSC
PRO
SBYTE0
SBYTE1
SBYTE2
SBYTE2
SBYTE1
SBYTE0
INTERNAL BUS
FCK
A
B
8
8
8
8
8
8
24
24
24
8
8
8
8
8
8
8
8
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(24)
(24)
FCKn
8
FIGURE 10. SINGLE-AXIS BLOCK DIAGRAM SHOWING MAJOR DATA PATHS
7266R1-111196-11
8
8
8
DIRECTION
7266R1-111196-12
D7
D6
D5
D4
D3
D2
D1
D0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
IOR
IOW
ADDRESS
DECODER
D0
D1
D2
D3
D4
D5
D6
D7
ISA BUS
PC AT/XT
I4
I6
I3
I7
I5
IOW
IOR
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
WR
RD
C/D
X/Y
CS
LS7266R1
4
5
6
7
8
9
10
11
FIGURE 11A. LS7266R1 INTERFACE EXAMPLES
AEN
A 1 - A 2 3
D 0 - D 7
R/W
LDS
DTACK
M C 6 8 0 0 0
M C 6 8 0 1 0
M C 6 8 H C 0 0 0
A D D R E S S
D E C O D E
CS
C/D
X/Y
D 0 - D 7
RD
WR
A1
A2
L S 7 2 6 6 R 1
FIGURE 11B. LS7266R1 INTERFACE EXAMPLES
#include<stdlib.h>
#include <stdio.h>
#include <conio.h>
#define XDATA(arg) (arg +0)
#define XCMD (arg) (arg + 1)
#define YDATA (arg) (arg +2)
#define YCMD (arg) (arg +3)
// RLD Reg.
#define RLD (arg) (arg | 0x80)
#define XRLD (arg) (arg | 0)
#define YRLD (arg) XRLD(arg)
#define Rst_BP 0x01
#define Rst_CNTR 0x02
#define Rst_FLAGS 0x04
#define Rst_E 0x06
#define Trf_PR_CNTR 0x08
#define Trf_CNTR_OL 0x10
#define Trf_PS0_PSC 0x18
7266R1-011598-13
//CMR Reg.
#define CMR(arg) (arg | 0xA0)
#define XCMR(arg) (arg | 0x20)
#define YCMR(arg) XCMR(arg)
#define BINCnt
0x00
#define BCDCnt
0x01
#define NrmCnt
0x00
#define RngLmt
0x02
#define NRcyc
0x04
#define ModN
0x06
#define NQDX
0x00
#define QDX1
0x08
#define QDX2
0x10
#define QDX4
0x18
//IOR Reg.
#define IOR(arg) (arg | 0xC0)
#define XIOR(arg) (arg | 0x40)
#define YIOR(arg) XIOR(arg)
#define DisAB
0x00
#define EnAB
0x01
#define LCNTR
0x00
#define LOL
0x02
#define RCNTR
0x00
#define ABGate
0x04
#define CYBW
0x00
#define CPBW
0x08
#define CB_UPDN
0x10
#define IDX_ERR
0x18
// IDR
#define IDR(arg) (arg | 0xE0)
#define XIDR(arg) (arg | 0x60)
#define YIDR(arg) XIDR(arg)
#define DisIDX
0x00
#define EnIDX
0x01
#define NIDX
0x00
#define PIDX
0x02
#define LIDX
0x00
#define RIDX
0x04
void Init_7266(int Addr);
/* Initialize 7266 as follows
Modulo N count mode for N = 0x123456
Binary Counting
Index on LCNTR/LOL Input
CY and BW outputs
RCNTR/ABG controls Counters
A and B Enabled
*/
void Init_7266(int Addr)
{
/Setup IOR Reg.
outp(XCMD(Addr),IOR(DisAB + LOL + ABGate + CYBW));
//Disable Counters and Set CY BW Mode
//Setup RLD Reg.
outp(XCMD(Addr),RLD(Rst_BP + Rst_FLAGS));
//Reset Byte Pointer(BP) And Flags
outp(XDATA(Addr),0x06);
//Load 6 to PR0 to setup Transfer to PS0
outp(XCMD(Addr),RLD(Rst_E + Trf_PS0_PSC));
//Reset E Flag and Transfer PR0 to PSC
outp(XCMD(Addr),RLD(Rst_BP + Rst_CNTR));
//Reset BP and Reset Counter
//Setup IDR Reg.
outp(XCMD(Addr),IDR(EnIDX + NIDX + LIDX));
//Enable Negative Index on LCNTR/LOL Input
//Setup CMR Reg.
outp(XCMD(Addr),CMR(BINCnt + ModN + QDX4)); //Set Binary Mondulo N Quadrature X4
C Sample Routines for Interfacing with LS7266R1
//Setup PR Reg. for Modulo N Counter to 0x123456
outp(XDATA(Addr),0x56);
//Least significant Byte first
outp(XDATA(Addr),0x34);
//then middle byte
outp(XDATA(Addr),0x12);
//then most significant byte
//Enable Counters
outp(XCMD(Addr),IOR(EnAB));
}
/* Write_7266_PR
Input: Addr has Address of 7266 counter.
Data: has 24 bit data to be written to PR register
*/
void Write_7266_PR(int Addr,unsigned long Data);
void Write_7266_PR(int Addr,unsigned long Data)
{
outp(XCMD(Addr),RLD(Rst_BP));
//Reset Byte Pointer to Synchronize Byte Writing
outp(XDATA(Addr),(unsigned char)Data);
Data >>= 8;
outp (XDATA(Addr),(unsigned char)Data);
Data >>= 8;
outp(XDATA(Addr),(unsigned char)Data);
}
/* Read_7266_OL
Input: Addr has Address of 7266 counter.
Output: Data returns 24 bit OL register value.
*/
unsigned long Read_7266_OL(int Addr);
unsigned long Read_7266_OL(int Addr)
{ unsigned long Data=0;
outp(XCMD(Addr),(RLD(Rst_BP + Trf_Cntr_OL)); //Reset Byte Pointer to Synchronize Byte reading and
Transferring of data from counters to OL.
Data |=(unsigned long)inp(XDATA(Addr));
//read byte 0 from OL
lrotr(Data,8);
//Rotate for next Byte
Data |=(unsigned long)inp(XDATA(Addr));
//read byte 1 from OL
lrotr(Data,8);
//Rotate for next Byte
Data |=(unsigned long)inp(XDATA(Addr)); //read byte 2 from OL
lrotr(Data,16);
//Rotate for last Byte
return(Data);
}
/*
Get_7266_Flags
Input: Addr has Address of 7266 counter.
returns Flags of counter
*/
unsigned char Get_7266_Flags(int Addr);
unsigned char Get_7266_Flags(int Addr)
{
return(inp(XCMD(Addr)));
}
7266R1-011598-14