32 BIT/DUAL 16 BIT BINARY UP COUNTER
WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
B4 OUT
B5 OUT
B0 IN
B1 IN
B2 IN
B7 OUT
B3 IN
TEST COUNT
S C A N R E S E T / L O A D
SCAN
E N A B L E
B6 OUT
V
DD
(+V)
(COUNT) B7 IN
B3 OUT
B6 IN
B2 OUT
B5 IN
B1 OUT
B4 IN
B0 OUT
R E S E T
CASCADE ENABLE OUT
Vss (-V)
LS7061
PIN ASSIGNMENT - TOP VIEW
FIGURE 1
LSI
FEATURES:
DC to 15MHz Count Frequency
Byte Multiplexer
DC to 1MHz Scan Frequency
+4.75V to +5.25V Operation (V
DD
- V
SS
)
Latch Provided for External High Speed Counter Byte,
Effectively Extending Count Frequency to 3.84GHz
Three-State Data Outputs, Bus and TTL Compatible
Inputs TTL and CMOS Compatible
Unique Cascade Feature Allows Multiplexing of Successive
Bytes of Data in Sequence in Multiple Counter Systems
LS7061, LS7063 (DIP);
LS7061-S, LS7063-S (SOIC) - See Figures 1 & 2
DESCRIPTION:
The LS7061/LS7063 is a MOS, 32 bit/dual 16 bit up counter. The
IC includes 40 latches, multiplexer, eight three-state binary data
output drivers and output cascading logic.
DESCRIPTION OF OPERATION:
32 (16) BIT BINARY UP COUNTER - LS7061 (LS7063)
The 32 (16) bit static ripple through counter increments on the
negative edge of the input count pulse. Maximum ripple time is
4s (2s) - transition count of 32 (16) ones to 32 (16) zeros.
Guaranteed count frequency is DC to 15MHz.
See Figure 8A (8B) for Block Diagram.
COUNT - LS7061, COUNT A - LS7063
Input count pulses to the 32 (first 16) bit counter may be applied
through this input. This input is the most significant bit of the ex-
ternal data byte.
COUNT B - LS7063
Count pulses may be applied to the last 16 bits of the binary
counter through this input. The counter advances on the negative
transition of these pulses.
RESET
All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 1s. RESET must be high for a minimum of
300ns before next valid count can be recorded. COUNT B must
be held low when RESET is brought low to ensure proper reset of
Counter B for LS7063.
TEST COUNT - LS7061
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.
7061/63-012703-1
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7061/7063
LATCHES - LS7061 (LS7063)
40 bits of latch are provided, eight for storage of the contents
of a high speed external prescaling counter and the remaining
32 for the contents of the counter data. All latches are loaded
when the LOAD input is brought low for a minimum of 1s
and kept low until a minimum of 4s (2s) has elapsed from
previous negative edge of count pulse (ripple time). Storage
of valid data occurs when LOAD is brought high for a mini-
mum of 250ns before next negative edge of count pulse or
RESET.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
B4 OUT
B5 OUT
B0 IN
B1 IN
B2 IN
B7 OUT
B3 IN
COUNT B
S C A N R E S E T / L O A D
SCAN
E N A B L E
B6 OUT
V
DD
(+V)
(COUNTA) B7 IN
B3 OUT
B6 IN
B2 OUT
B5 IN
B1 OUT
B4 IN
B0 OUT
R E S E T
CASCADE ENABLE OUT
Vss (-V)
LS7063
PIN ASSIGNMENT - TOP VIEW
FIGURE 2
LSI
UL
A3800
January 2003
SCAN COUNTER AND DECODER
The scan counter is reset to the least significant byte position
(State 1) when SCAN RESET input is brought low for a mini-
mum of 1s. The scan counter is enabled for counting as long
as the ENABLE input is held low. The counter advances to the
next significant byte position on each negative transition of the
SCAN pulse. When the scan counter advances to State 6 it dis-
ables the Output Drivers and stops in that state until
SCAN RESET is again brought low.
SCAN
When the scan counter is enabled, each negative transition of
this input advances the scan counter to its next state. When
SCAN is low the Data Outputs are disabled. When SCAN is
brought high the Data Outputs are enabled and present the
latched counter data corresponding to the present state of the
scan counter. Therefore, in microprocessor applications, the
Data Output Bus may be utilized for other activities while new
data is propagating to the outputs. This positive SCAN pulse
can be viewed as a "Place the next byte on my bus" instruction
from the microprocessor. Minimum positive and negative pulse
widths of 500ns for the SCAN signal are required for scan
counter operation.
SCAN RESET/LOAD
When this input is brought low for a minimum of 1s, the scan
counter is reset to State 1, the least significant byte position,
and the latches are simultaneously loaded with new count
information.
ENABLE
When this input is high, the scan counter and the Data Outputs are
disabled. When ENABLE is low, the scan counter and Data Out-
puts are enabled for normal operation. Transition of this input
should only be made while the SCAN input is in a low state in order
to prevent false clocking of the scan counter.
CASCADE ENABLE
This output is normally high. It transitions low and stays low when
the scan counter advances to State 6. In a multiple counter system
this output is connected to the ENABLE input of the next counter in
the cascade string. The SCAN input and SCAN RESET/LOAD in-
put are carried to all the counters in the "Cascade". Counter 1 then
presents its bytes of data to the Output Bus on each positive transi-
tion of the SCAN pulse as previously discussed. When State 6 of
Counter 1 is achieved, Counter 2 presents its data to the Output
Bus. This sequence continues until all counters in the cascade
have been addressed. See Figure 5 for an illustration of a 3 device
cascade design. This output is TTL and CMOS compatible.
THREE-STATE DATA OUTPUT DRIVERS
The eight Data Output Drivers are disabled when either ENABLE
input is high, the scan counter is in State 6, or the SCAN input is
low. The Output Drivers are TTL and Bus compatible.
7061/63-012703-2
valid
valid
valid
valid
LSB
LSB+1
t
DCE
t
DOE
LSB +2
LSB+3
t
DOD
FIGURE 3. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM
t
DCE
t
RSCPW
t
RSCR
t
SCPW
t
SCPW
SCAN RESET
ENABLE
SCAN
ST1 (int.)
ST2 (int.)
ST3 (int.)
ST4 (int.)
ST5 (int.)
ENABLE (int.)
CASCADE ENABLE
DATA OUTPUTS
ENABLE (int.)
ST6 (int.)
valid
MSB
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
SYMBOL
VALUE
UNIT
StorageTemperature
T
STG
-55 to +150
C
Operating Temperature
T
A
0 to +70
C
Voltage (any pin to V
SS
)
V
IN
+10 to -0.3
V
DC ELECTRICAL CHARACTERISTICS:
(V
DD
= +5V 5%, V
SS
= 0V, T
A
= 0C to + 70C unless otherwise noted.)
PARAMETER
SYMBOL
Min
MAX
UNIT
CONDITIONS
Power Supply Current
I
DD
-
15
mA
At Maximum Operating Frequency
V
DD
= Max, Outputs No Load
Input High Voltage
V
IH
+3.5
V
DD
V
-
Input Low Voltage
V
IL
0
+0.6
V
-
Output High Voltage
CASCADE ENABLE
V
OH
V
DD
- 0.2
-
V
I
O
= 0, V
DD
= Min
+2.4
-
V
I
O
= -100A, V
DD
= Min
B0 - B7
+2.4
-
V
I
O
= -260A, V
DD
= Min
+2.0
-
V
I
O
= -750A, V
DD
= Min
Output Low Voltage
CASCADE ENABLE
V
OL
-
+0.2
V
I
O
= 0, V
DD
= Min
+0.4
V
I
O
= 1.6mA, V
DD
= Min
B0 - B7
+0.4
V
I
O
= 1.6mA, V
DD
= Min
Output Source Current
Isource
3.0
-
mA
V
O
= +1.2V, V
DD
= Min
B0 - B7 Outputs
4.8
-
mA
V
O
= +0.8V, V
DD
= Min
7.3
-
mA
V
O
= +0.4V, V
DD
= Min
Output Sink Current
Isink
5.7
-
mA
V
O
= +1.2V, V
DD
= Min
B0 - B7 Outputs
4.0
-
mA
V
O
= +0.8V, V
DD
= Min
2.2
-
mA
V
O
= +0.4V, V
DD
= Min
Output Leakage Current
I
OL
-
1
A
V
O
= +0.4V to +2.4V,V
DD
= Min
B0 - B7 (Off State)
Input Capacitance
C
IN
-
6
pF
T
A
= 25C, f = 1MHz
Output Capacitance
C
OUT
-
12
pF
T
A
= 25C, f = 1MHz
Input Leakage Current
I
LI
-
1
A
V
DD
= Max
ENABLE, RESET, SCAN
Input Current
*SCAN RESET/LOAD
I
IH
-
-2.5
A
V
DD
= Max, V
IH
= +3.5
- -5
A
V
DD
= Max, V
IL
= 0
**B0 - B7, COUNT B,
I
IH
-
5
A
V
DD
= Max, V
IH
= +3.5
TEST COUNT
I
IL
-
1
A
V
DD
= Max, V
IL
= 0
*Input has internal pull-up resistor to V
DD
** Inputs have internal pull-down resistor to V
SS
7061/63-012703-3
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
DYNAMIC ELECTRICAL CHARACTERISTICS: (Refer to Figure 3, Timing Diagram)
(V
DD
= +5V 5%, V
SS
= 0V, T
A
= 0C to +70C unless otherwise noted.)
PARAMETER
SYMBOL
MIN
MAX
UNIT
CONDITIONS
Count Frequency
fc
DC
15
MHz
-
(All Count inputs)
Count Pulse Width
t
CPW
30
-
ns
Measured at 50% point,
(All Count Inputs)
Max
t
r,
t
f
= 10ns
Count Rise & Fall time
t
r,
t
f
-
30
s
-
(Pins 2, 16)
Count Ripple Time
t
CR
-
4
s
Transition from 32 ones to 32 zeros
(Pin 2 - LS7061)
from negative edge of count pulse
Count Ripple Time
t
CR
-
2
s
Transition of 16 bits from all ones to all
(Pin 13 - LS7061) zeros from negative edge of count pulse
(Pins 2, 13 - LS7063)
RESET Pulse Width
t
RPW
500
-
ns
Measured at 50% point,
(All Counter Stages
Max
t
r
,
t
f
= 200ns
Fully Reset)
RESET Removal Time
t
RR
-
250
ns
Measured from RESET signal at V
IH
(Reset Removed From
All Counter Stages)
SCAN Frequency
f
SC
-
1
MHz
-
SCAN Pulse Wildth
t
SCPW
500
-
ns
Measured at 50% point,
Max
t
r
,
t
f
= 100ns
SCAN RESET/LOAD
t
RSCPW
1
-
s
Measured at 50% point,
Pulse Width
Max
t
r
,
t
f
= 200ns
(All latches loaded and
Scan Counter Reset to
Least Significant Byte)
SCAN RESET/LOAD
t
RSCR
-
250
ns
Measured from SCAN RESET/
Removal Time
LOAD at V
IH
(Reset Removed from
Scan Counter; Load
Command Removed
From Latches)
Output Disable
t
DOD
-
200
ns
Transition to Output High
Delay Time
Impedance State Measured
(B0 - B7)
From Scan at V
IL
or ENABLE at V
IH
Output ENABLE
t
DOE
-
200
ns
Transition to Valid On State
Delay Time
Measured from Scan at V
IH
(B0 - B7)
and ENABLE at V
IL
; Delay to
Valid Data Levels for C
OL
= 10pF
and one TTL Load or Valid Data
Currents for High Capacitance Loads
Output Delay Time
t
DCE
-
300
ns
Negative Transition from Scan at V
IL
CASCADE ENABLE
and ST5 of Scan Counter or Positive
Transition From SCAN RESET/LOAD at
V
IL
to Valid Data Levels for C
OL
= 10pF
and one TTL Load
7061/63-012703-4
FIGURE 4. COUNTER TIMING DIAGRAM
RESET
COUNT
LOAD
t
RPW
t
RR
+ t
CPW
t
RSCPW
t
RSCR
t
CR
t
CPW
t
RPW
t
CPW
t
RR
+t
CPW
A
EN SC RESET SC
CE
B
EN SC RESET SC
CE
C
EN SC RESET SC
CE
OUTPUT DATA BUS
ENABLE
SCAN RESET
SCAN
FIGURE 5. ILLUSTRATION OF A 3 DEVICE CASCADE
END OF SCAN
7061/63-012703-5
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