32 BIT BINARY UP COUNTER
WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
LSI
PIN ASSIGNMENT - TOP VIEW
SCAN
ENABLE
SCAN RESET/LOAD
TEST COUNT
B7 OUT
B6 OUT
B5 OUT
B4 OUT
V
DD
(+V)
ALT COUNT
B3 OUT
B2 OUT
B1 OUT
B0 OUT
RESET
CASCADE EN OUT
V
SS
(-V)
FIGURE 1
LS7060C
COUNT
FEATURES:
DC to 50MHz Count Frequency
Byte Multiplexer
DC to 10MHz Byte Output Scan Frequency
+4.75V to +5.25V Operation (V
DD
- V
SS
)
Three-State Data Outputs; Bus, TTL and CMOS Compatible
Inputs TTL and CMOS Compatible
Unique Cascade Feature Allows Multiplexing of
Successive Bytes of Data in Sequence in Multiple
Counter Systems
Low Power Dissipation
LS7060C (DIP); LS7060C-S (SOIC) - See Figure 1
LS7061C (DIP); LS7061C-S (SOIC) - See Figure 2
DESCRIPTION:
The LS7060C/LS7061C are CMOS Silicon Gate, 32 bit Up
Counters. The ICs include latches, multiplexer, byte output se-
quencer, eight three-state binary data output drivers and output
cascading logic.
DESCRIPTION OF OPERATION:
32 BIT BINARY UP COUNTER - LS7060C (LS7061C)
The 32 bit static ripple through counter increments on the neg-
ative edge of the input count pulse. Maximum ripple time is 20ns
transition count of 32 ones to 32 zeros.
Guaranteed count frequency is DC to 50MHz.
See Figure 9A (9B) for Block Diagram.
COUNT, ALT COUNT (LS7060C)
Input count pulses to the 32 bit counter may be applied through
either of these two inputs. The ALT COUNT input circuitry con-
tains a Schmitt trigger network which allows proper counting with
"infinitely" long clock edges. A high applied to either of these two
inputs inhibits counting.
COUNT (LS7061C)
Input count pulses to the 32 bit counter may be applied through
this input. This input is the most significant bit of the external data
byte.
RESET
All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 20ns. RESET must be high for a minimum of
10ns before next valid count can be recorded.
TEST COUNT
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.
NOTE: LS7060C and LS7061C can directly replace LS7060 and
LS7061 in all existing applications.
November 2002
7060C/61C-110702-1
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
LS7060C
LS7061C
UL
A3800
LATCHES
32 bits of latch are provided for storage of counter data for the
LS7060C. 40 bits of latch are provided for the LS7061C of which
eight are for storage of a high speed external prescaling counter
and the remaining 32 are for the contents of the chip counter
data. All latches are loaded when the LOAD input is brought low
for a minimum of 10ns and kept low until a minimum of 20ns has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when LOAD is brought high for a
minimum of 20ns before next negative edge of count pulse or
RESET.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
B4 OUT
B5 OUT
B0 IN
B1 IN
B2 IN
B7 OUT
B3 IN
TEST COUNT
SCAN RESET/LOAD
SCAN
ENABLE
B6 OUT
V
DD
(+V)
(COUNT) B7 IN
B3 OUT
B6 IN
B2 OUT
B5 IN
B1 OUT
B4 IN
B0 OUT
R E S E T
CASCADE ENABLE OUT
Vss (-V)
PIN ASSIGNMENT - TOP VIEW
FIGURE 2
LSI
L S 7 0 6 1 C
ADVANCE INFORMATION
SCAN COUNTER AND DECODER
The scan counter is reset to the least significant byte position
(State 1) when SCAN RESET input is brought low for a mini-
mum of 10ns. The scan counter is enabled for counting as long
as the ENABLE input is held low. The counter advances to the
next significant byte position on each negative transition of the
SCAN pulse. When the scan counter advances to State 5 for
the LS7060C or Stage 6 for the LS7061C it disables the Output
Drivers and stops in that state until SCAN RESET is again
brought low.
SCAN
When the scan counter is enabled, each negative transition of
this input advances the scan counter to its next state. When
SCAN is low the Data Outputs are disabled. When SCAN is
brought high the Data Outputs are enabled and present the
latched counter data corresponding to the present state of the
scan counter. Therefore, in microprocessor applications, the
Data Output Bus may be utilized for other activities while new
data is propagating to the outputs. This positive SCAN pulse
can be viewed as a "Place the next byte on my bus" instruction
from the microprocessor. Minimum positive and negative pulse
widths of 10ns for the SCAN signal are required for scan
counter operation.
SCAN RESET/LOAD
When this input is brought low for a minimum of 10ns, the scan
counter is reset to State 1, the least significant byte position,
and the latches are simultaneously loaded with new count
information.
ENABLE
When this input is high, the scan counter and the Data Outputs are
disabled. When ENABLE is low, the scan counter and Data Outputs
are enabled for normal operation. Transition of this input should
only be made while the SCAN input is in a low state in order to pre-
vent false clocking of the scan counter.
CASCADE ENABLE
This output is normally high. It transitions low and stays low when
the scan counter advances to State 5 for LS7060C and State 6 for
LS7061C. In a multiple counter system this output is connected to
the ENABLE input of the next counter in the cascade string. The
SCAN input and SCAN RESET/LOAD input are carried to all the
counters in the "Cascade". Counter 1 then presents its bytes of data
to the Output Bus on each positive transition of the SCAN pulse as
previously discussed. When State 5 for LS7060C or State 6 for
LS7061C of Counter 1 is achieved, Counter 2 presents its data to
the Output Bus. This sequence continues until all counters in the
cascade have been addressed. See Figure 5 for an illustration of a
3 device cascade design. This output is TTL and CMOS
compatible.
THREE-STATE DATA OUTPUT DRIVERS
The eight Data Output Drivers are disabled when either ENABLE
input is high, the scan counter is in State 5 for LS7060C and State 6
for LS7061C, or the SCAN input is low. The Output Drivers are TTL
and Bus compatible.
POWER-ON-RESET
Upon the application of power to the IC, the counters and latches
are set to Logic 0 and the scan counter is set to State 1.
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
SYMBOL
VALUE
UNIT
StorageTemperature
T
STG
-55 to +150
C
Operating Temperature
T
A
0 to +70
C
Voltage (any pin to V
SS
)
V
IN
+10 to -0.3
V
DC ELECTRICAL CHARACTERISTICS:
(V
DD
= +5V 5%, V
SS
= 0V, T
A
= 0C to +70C unless otherwise noted.)
PARAMETER
SYMBOL
MIN
MAX
UNIT
CONDITIONS
Quiescent Power Supply
I
DD
-
0.5
mA
V
DD
= Max, Outputs No Load,
Current
Frequency
Power Supply Current
I
DD
-
4
mA
15 MHz Operating Frequency
V
DD
= Max, Outputs No Load
Power Supply Current
I
DD
-
8
mA
At Maximum Operating Frequency
V
DD
= Max, Outputs No Load
Input High Voltage
V
IH
+3.5
V
DD
V
-
Input Low Voltage
V
IL
0
+0.6
V
-
Output High Voltage
CASCADE ENABLE
V
OH
+2.4
-
V
I
O
= -6mA, V
DD
= Min
B0 - B7
V
OH
+2.4
-
V
I
O
= -33mA, V
DD
= Min
Output Low Voltage
CASCADE ENABLE
V
OL
-
+0.4
V
I
O
= 3mA, V
DD
= Min
B0 - B7
V
OL
-
+0.4
V
I
O
= 10mA, V
DD
= Min
Output Source Current
Isource
-34
-
mA
V
O
= +1.2V, V
DD
= Min
B0 - B7 Outputs
-36
-
mA
V
O
= +0.8V, V
DD
= Min
-38
-
mA
V
O
= +0.4V, V
DD
= Min
Output Sink Current
Isink
25
-
mA
V
O
= +1.2V, V
DD
= Min
B0 - B7 Outputs
20
-
mA
V
O
= +0.8V, V
DD
= Min
10
-
mA
V
O
= +0.4V, V
DD
= Min
Output Leakage Current
I
OL
-
10
nA
V
O
= +0.4V to +2.4V, V
DD
= Min
B0 - B7 (Off State)
Input Capacitance
C
IN
-
6
pF
T
A
= 25C, f = 1MHz
Output Capacitance
C
OUT
-
12
pF
T
A
= 25C, f = 1MHz
Input Leakage Current
I
LI
-
10
nA
V
DD
= Max
ENABLE, RESET, SCAN
7060C/61C-110702-2
DYNAMIC ELECTRICAL CHARACTERISTICS:
(V
DD
= +5V 5%, V
SS
= 0
V
, T
A
= 0C to +70C unless otherwise noted.)
PARAMETER
SYMBOL
MIN
MAX
UNIT
CONDITIONS
Count Frequency
fc
DC
50
MHz
-
(All Count inputs)
Count Pulse Width
t
CPW
10
-
ns
Measured at 50% point,
(All Count Inputs)
Max tr, t
f
= 1ns
Count Ripple Time
t
CR
-
20
ns
Transition from 32 ones to 32 zeros
from negative edge of count pulse
Reset Pulse Width
t
RPW
20
-
ns
Measured at 50% point
(All Counter Stages
Max t
r
, t
f
= 10ns
Fully Reset)
RESET Removal Time
t
RR
-
10
ns
Measured from RESET signal at V
IH
(Reset Removed From
All Counter Stages)
SCAN Frequency
f
SC
-
10
MHz
SCAN Pulse Width
t
SCPW
50
-
ns
Measured at 50% point
Max t
r
, t
f
= 10ns
SCAN RESET/LOAD
t
RSCPW
10
-
ns
Measured at 50% point
Pulse Width
Max t
r
, t
f
= 5ns
(All latches loaded and
Scan Counter Reset to
Least Significant Byte)
SCAN RESET/LOAD
t
RSCR
-
10
ns
Measured from
Removal Time
SCAN RESET/LOAD at V
IH
(Reset Removed from
Scan Counter; Load
Command Removed
From Latches)
Output Disable
t
DOD
-
5
ns
Transition to Output High
Delay Time
Impedance State Measured
(B0 - B7)
From Scan at V
IL
or
ENABLE at V
IH
Output ENABLE
t
DOE
-
5
ns
Transition to Valid On State
Delay Time
Measured from Scan at V
IH
(B0 - B7)
and ENABLE at V
IL
; Delay to
Valid Data Levels for C
OL
= 10pF
and one TTL Load or Valid Data
Currents for High Capacitance Loads
Output Delay Time
t
DCE
-
10
ns
Negative Transition from Scan at V
IL
CASCADE ENABLE
and ST5 of Scan Counter or Positive
Transition From SCAN RESET/LOAD at
V
IL
to Valid Data Levels for C
OL
= 12pF
and one TTL Load
SYMBOL MIN MAX UNIT CONDITIONS
INPUT CURRENT
*SCAN RESET/LOAD
I
IH
-
-3.5
A
V
DD
= Max, V
IH
= +3.5V
I
IL
-
-5
A
V
DD
= Max, V
IL
= 0V
**All Count inputs
I
IH
-
5
A
V
DD
= Max, V
IH
= +3.5V
I
IL
-
1
A
V
DD
= Max, V
IL
= 0.35V
*Input has internal pull-up resistor to V
DD
** Inputs have internal pull-down resistor to V
SS
7060C/61C-121901-3
valid
valid
valid
valid
LSB
LSB+1
t
DCE
t
DOE
LSB +2
MSB
t
DOD
FIGURE 3A. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM FOR LS7060C
t
DCE
t
RSCPW
t
RSCR
t
SCPW
t
SCPW
SCAN RESET
ENABLE
SCAN
ST1 (int.)
ST2 (int.)
ST3 (int.)
ST4 (int.)
ST5 (int.)
ENABLE (int.)
CASCADE ENABLE
DATA OUTPUTS
valid
valid
valid
valid
LSB
LSB+1
t
DCE
t
DOE
LSB +2
LSB+3
t
DOD
FIGURE 3B. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM FOR LS7061C.
t
DCE
t
RSCPW
t
RSCR
t
SCPW
t
SCPW
SCAN RESET
ENABLE
SCAN
ST1 (int.)
ST2 (int.)
ST3 (int.)
ST4 (int.)
ST5 (int.)
ENABLE (int.)
CASCADE ENABLE
DATA OUTPUTS
ST6 (int.)
valid
MSB
7060C/62C-121801-4
FIGURE 4. COUNTER TIMING DIAGRAM
RESET
COUNT
LOAD
t
RPW
t
RR
+ t
CPW
t
RSCPW
t
RSCR
t
CR
t
CPW
t
RPW
t
CPW
t
RR+tCPW
A
EN SC RESET SC
CE
B
EN SC RESET SC
CE
C
EN SC RESET SC
CE
OUTPUT DATA BUS
ENABLE
SCAN RESET
SCAN
FIGURE 5. ILLUSTRATION OF A 3 DEVICE CASCADE
END OF SCAN
7060C/61C-121901-5
S C A N R E S E T
E N A B L E
SCAN
CASCADE ENABLE A
CASCADE ENABLE B
CASCADE ENABLE C
DATA BYTE ON BUS
PACKAGE
A
1
2
3
4
5
1
2
3
4
5
B
1
2
3
4
5
C
FIGURE 6. TIMING DIAGRAM FOR THE 3 DEVICE CASCADE
(END OF SCAN)
PDF 
ZIP