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Электронный компонент: LSH33

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DEVICES INCORPORATED
Special Arithmetic Functions
08/16/2000LDS.33-O
1
LSH33
32-bit Barrel Shifter with Registers
u
u
u
u
u 32-bit Input, 32-bit Output Multi-
plexed to 16 Lines
u
u
u
u
u Full 0-31 Position Barrel Shift
Capability
u
u
u
u
u Integral Priority Encoder for 32-bit
Floating Point Normalization
u
u
u
u
u Sign-Magnitude or Two's Comple-
ment Mantissa Representation
u
u
u
u
u 32-bit Linear Shifts with Sign or
Zero Fill
u
u
u
u
u Independent Priority Encoder
Outputs for Block Floating Point
u
u
u
u
u
68-pin PLCC, J-Lead
FEATURES
DESCRIPTION
LSH33
32-bit Barrel Shifter with Registers
DEVICES INCORPORATED
LSH33 B
LOCK
D
IAGRAM
The LSH33 is a 32-bit high speed
shifter designed for use in floating
point normalization, word pack/
unpack, field extraction, and similar
applications. It has 32 data inputs,
and 16 output lines. Any shift con-
figuration of the 32 inputs, including
circular (barrel) shifting, left shifts
with zero fill, and right shifts with
sign extension are possible. In addi-
tion, a built-in priority encoder is
provided to aid floating point normal-
ization.
Input/Output registers provide
complete pipelined operation. Both
have independent bypass paths for
complete flexibility. When FTI = 1,
the input registers are bypassed.
Likewise, when FTO= 1, the output
registers are bypassed.
SHIFT ARRAY
The 32 inputs, which can be regis-
tered, to the LSH33 are applied to a
32-bit shift array. The 32 outputs,
which can also be registered, of this
array are then multiplexed down to
16 lines for presentation at the device
outputs. The array may be configured
such that any contiguous 16-bit field
(including wraparound of the 32
inputs) may be presented to the
output pins under control of the shift
code field (wrap mode). Alterna-
tively, the wrap feature may be
disabled, resulting in zero or sign bit
fill, as appropriate (fill mode). The
shift code control assignments and the
resulting input to output mapping for
the wrap mode are shown in Table 1.
Essentially the LSH33 is configured as
a left shift device. That is, a shift code
of 00000
2
results in no shift of the
input field. A code of 00001
2
provides
an effective left shift of 1 position, etc.
When viewed as a right shift, the shift
code corresponds to the two's comple-
ment of the shift distance, i.e., a shift
code of 11111
2
(1
10
) results in a right
shift of one position, etc.
When not in the wrap mode, the
LSH33 fills bit positions for which
there is no corresponding input bit.
The fill value and the positions filled
depend on the RIGHT/LEFT (R/L)
direction pin. This pin is a don't care
input when in wrap mode. For left
shifts in fill mode, lower bits are filled
with zero as shown in Table 2. For
right shifts, however, the SIGN input
is used as the fill value. Table 3
depicts the bits to be filled as a
function of shift code for the right shift
case. Note that the R/L input changes
only the fill convention, and does not
affect the definition of the shift code.
16
OE
MS/LS
32-bit
BARREL
SHIFT
ARRAY
16
2:1
32:5
PRIORITY
ENCODE
32
5
32
SIGN
NORM
RIGHT/LEFT
FILL/WRAP
5
G
G
2:1
G
G
2:1
2:1
2:1
2:1
ENO
CLK
ENI
CLK
FTO
FTI
G
2:1
5
I
31
-I
0
Y
15
-Y
0
SI/O
4
-SI/O
0
16
08/16/2000LDS.33-O
2
Special Arithmetic Functions
DEVICES INCORPORATED
LSH33
32-bit Barrel Shifter with Registers
T
ABLE
1.
W
RAP
M
ODE
S
HIFT
C
ODE
D
EFINITIONS
Shift Code
Shift Code
Shift Code
Shift Code
Shift Code
Y
Y
Y
Y
Y
31
31
31
31
31
Y
Y
Y
Y
Y
30
30
30
30
30
Y
Y
Y
Y
Y
29
29
29
29
29
Y
Y
Y
Y
Y
16
16
16
16
16
Y
Y
Y
Y
Y
15
15
15
15
15
Y
Y
Y
Y
Y
2
2
2
2
2
Y
Y
Y
Y
Y
1
1
1
1
1
Y
Y
Y
Y
Y
0
0
0
0
0
00000
I
31
I
30
I
29
I
16
I
15
I
2
I
1
I
0
00001
I
30
I
29
I
28
I
15
I
14
I
1
I
0
I
31
00010
I
29
I
28
I
27
I
14
I
13
I
0
I
31
I
30
00011
I
28
I
27
I
26
I
13
I
12
I
31
I
30
I
29
01111
I
16
I
15
I
14
I
1
I
0
I
19
I
18
I
17
10000
I
15
I
14
I
13
I
0
I
31
I
18
I
17
I
16
10001
I
14
I
13
I
12
I
31
I
30
I
17
I
16
I
15
10010
I
13
I
12
I
11
I
30
I
29
I
16
I
15
I
14
11100
I
3
I
2
I
1
I
20
I
19
I
6
I
5
I
4
11101
I
2
I
1
I
0
I
19
I
18
I
5
I
4
I
3
11110
I
1
I
0
I
31
I
18
I
17
I
4
I
3
I
2
11111
I
0
I
31
I
30
I
17
I
16
I
3
I
2
I
1
T
ABLE
2.
F
ILL
M
ODE
S
HIFT
C
ODE
D
EFINITIONS
-- L
EFT
S
HIFT
In fill mode, as in wrap mode, the shift
code input represents the number of
shift positions directly for left shifts,
but the two's complement of the shift
code results in the equivalent right
shift. However, for fill mode the R/L
input can be viewed as the most
significant bit of a 6-bit two's comple-
ment shift code, comprised of R/L
concatenated with the SI
4
SI
0
lines.
Thus, a positive shift code (R/L = 0)
results in a left shift of 031 positions,
and a negative code (R/L = 1) a right
shift of up to 32 positions. The LSH33
can thus effectively select any contigu-
ous 32-bit field out of a (sign extended
and zero filled) 96-bit "input."
OUTPUT MULTIPLEXER
The shift array outputs can be regis-
tered and then applied to a 2:1 multi-
plexer controlled by the MS/LS select
line. This multiplexer makes available
at the output pins either the most
significant or least significant 16
outputs of the shift array.
PRIORITY ENCODER
The 32-bit input bus drives a priority
encoder which is used to determine
the first significant position for
purposes of normalization. The
priority encoder produces a five-bit
code representing the location of the
first non-zero bit in the input word.
Code assignment is such that the
priority encoder output represents the
number of shift positions required to
left align the first non-zero bit of the
input word. Prior to the priority
encoder, the input bits are individu-
ally exclusive OR'ed with the SIGN
input. This allows normalization in
floating point systems using two's
complement mantissa representation.
A negative value in two's complement
representation will cause the exclusive
OR gates to invert the input data to
the encoder. As a result, the leading
significant digit will always be "1."
Shift Code
Shift Code
Shift Code
Shift Code
Shift Code
Y
Y
Y
Y
Y
31
31
31
31
31
Y
Y
Y
Y
Y
30
30
30
30
30
Y
Y
Y
Y
Y
29
29
29
29
29
Y
Y
Y
Y
Y
16
16
16
16
16
Y
Y
Y
Y
Y
15
15
15
15
15
Y
Y
Y
Y
Y
2
2
2
2
2
Y
Y
Y
Y
Y
1
1
1
1
1
Y
Y
Y
Y
Y
0
0
0
0
0
00000
I
31
I
30
I
29
I
16
I
15
I
2
I
1
I
0
00001
I
30
I
29
I
28
I
15
I
14
I
1
I
0
0
00010
I
29
I
28
I
27
I
14
I
13
I
0
0
0
00011
I
28
I
27
I
26
I
13
I
12
0
0
0
01111
I
16
I
15
I
14
I
1
I
0
0
0
0
10000
I
15
I
14
I
13
I
0
0
0
0
0
10001
I
14
I
13
I
12
0
0
0
0
0
10010
I
13
I
12
I
11
0
0
0
0
0
11100
I
3
I
2
I
1
0
0
0
0
0
11101
I
2
I
1
I
0
0
0
0
0
0
11110
I
1
I
0
0
0
0
0
0
0
11111
I
0
0
0
0
0
0
0
0
DEVICES INCORPORATED
Special Arithmetic Functions
08/16/2000LDS.33-O
3
LSH33
32-bit Barrel Shifter with Registers
T
ABLE
3.
F
ILL
M
ODE
S
HIFT
C
ODE
D
EFINITIONS
-- R
IGHT
S
HIFT
T
ABLE
4.
P
RIORITY
E
NCODER
F
UNCTION
T
ABLE
I
I
I
I
I
31
31
31
31
31
I
I
I
I
I
30
30
30
30
30
I
I
I
I
I
29
29
29
29
29
I
I
I
I
I
16
16
16
16
16
I
I
I
I
I
15
15
15
15
15
I
I
I
I
I
2
2
2
2
2
I
I
I
I
I
1
1
1
1
1
I
I
I
I
I
0
0
0
0
0
Shift Code
Shift Code
Shift Code
Shift Code
Shift Code
1
X
X
X
X
X
X
X
00000
0
1
X
X
X
X
X
X
00001
0
0
1
X
X
X
X
X
00010
0
0
0
1
X
X
X
X
01111
0
0
0
0
1
X
X
X
10000
0
0
0
0
0
X
X
X
10001
0
0
0
0
0
0
1
X
11110
0
0
0
0
0
0
0
1
11111
0
0
0
0
0
0
0
0
11111
This affects only the encoder inputs;
the shift array always operates on the
raw input data. The priority encoder
function table is shown in Table 4.
NORMALIZE MULTIPLEXER
The NORM input, when asserted,
results in the priority encoder output
driving the internal shift code inputs
directly. When using the NORM
function, the LSH33 should be placed
in fill mode, with the R/L input low.
When NORM is high (not asserted),
the SI/O
4
SI/O
0
port acts as the shift
code input to the shifter.
APPLICATIONS EXAMPLES
Normalization of mantissas up to 32
bits can be accomplished directly by a
single LSH33. To do this, the NORM
input is asserted, and fill mode and
left shift are selected. The normalized
mantissa is then available at the
device output in two 16-bit segments,
under the control of the output data
multiplexer select, the MS/LS signal.
If it is desirable to avoid the necessity
of multiplexing output data in 16-bit
segments, two LSH33 devices can be
used in parallel. Both devices receive
the same input word, with the MS/LS
select line of one wired high, and the
other low. Each device will then
independently determine the shift
distance required for normalization,
and the full 32 bits of output data will
be available simultaneously.
Shift Code
Shift Code
Shift Code
Shift Code
Shift Code
Y
Y
Y
Y
Y
31
31
31
31
31
Y
Y
Y
Y
Y
30
30
30
30
30
Y
Y
Y
Y
Y
29
29
29
29
29
Y
Y
Y
Y
Y
16
16
16
16
16
Y
Y
Y
Y
Y
15
15
15
15
15
Y
Y
Y
Y
Y
2
2
2
2
2
Y
Y
Y
Y
Y
1
1
1
1
1
Y
Y
Y
Y
Y
0
0
0
0
0
00000
S
S
S
S
S
S
S
S
00001
S
S
S
S
S
S
S
I
31
00010
S
S
S
S
S
S
I
31
I
30
00011
S
S
S
S
S
I
31
I
30
I
29
01111
S
S
S
S
S
I
19
I
18
I
17
10000
S
S
S
S
I
31
I
18
I
17
I
16
10001
S
S
S
I
31
I
30
I
17
I
16
I
15
10010
S
S
S
I
30
I
29
I
16
I
15
I
14
11100
S
S
S
I
20
I
19
I
6
I
5
I
4
11101
S
S
S
I
19
I
18
I
5
I
4
I
3
11110
S
S
I
31
I
18
I
17
I
4
I
3
I
2
11111
S
I
31
I
30
I
17
I
16
I
3
I
2
I
1
08/16/2000LDS.33-O
4
Special Arithmetic Functions
DEVICES INCORPORATED
LSH33
32-bit Barrel Shifter with Registers
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
OH
Output High Voltage
V
CC
= Min., I
OH
= 2.0 mA
2.4
V
V
OL
Output Low Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.4
V
V
IH
Input High Voltage
2.0
V
CC
V
V
IL
Input Low Voltage
(Note 3)
0.0
0.8
V
I
IX
Input Current
Ground
V
IN
V
CC
(Note 12)
20
A
I
OZ
Output Leakage Current
Ground
V
OUT
V
CC
(Note 12)
20
A
I
CC1
V
CC
Current, Dynamic
(Notes 5, 6)
10
30
mA
I
CC2
V
CC
Current, Quiescent
(Note 7)
1.5
mA
Storage temperature ........................................................................................................... 65C to +150C
Operating ambient temperature ........................................................................................... 55C to +125C
V
CC
supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Mode
Temperature Range (Ambient)
Supply
Voltage
Active Operation, Commercial
0C to +70C
4.75 V
V
CC
5.25 V
Active Operation, Military
55C to +125C
4.50 V
V
CC
5.50 V
DEVICES INCORPORATED
Special Arithmetic Functions
08/16/2000LDS.33-O
5
LSH33
32-bit Barrel Shifter with Registers
1234567890123
1234567890123
1234567890123
1234567890123
1234567890123
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LSH33-40*
Y
15
-Y
0
SO
4
-SO
0
28
28
28
--
73
/
40
55
/
--
52
--
52
--
28
--
28
28
28
--
73
/
40
55
/
--
52
--
52
--
28
--
SWITCHING CHARACTERISTICS -- C
OMMERCIAL
O
PERATING
R
ANGE
(0C to +70C)
G
UARANTEED
M
AXIMUM
C
OMBINATIONAL
D
ELAYS
Notes 9, 10 (ns)
To Output
From Input
FTI = 0, FTO = 0
CLK
MS/LS
FTI = 0, FTO= 1
CLK (NORM = 0/1)
SI
4
-SI
0
R/L, F/W
MS/LS
FTI = 1, FTO = 0
CLK
MS/LS
FTI = 1, FTO = 1
I
31
-I
0
, SIGN
(NORM = 0/1)
SI
4
-SI
0
R/L, F/W
MS/LS
LSH33-30
Y
15
-Y
0
SO
4
-SO
0
24
24
24
--
58
/
30
42
/
--
40
--
40
--
24
--
24
24
24
--
58
/
30
42
/
--
40
--
40
--
24
--
LSH33-20*
Y
15
-Y
0
SO
4
-SO
0
15
15
15
--
20
/
20
20
/
--
20
--
20
--
15
--
15
15
15
--
20
/
20
20
/
--
20
--
20
--
15
--
Input
I
31
-I
0
, SIGN
SI
4
-SI
0
R/L, F/W
ENI, ENO
G
UARANTEED
M
INIMUM
S
ETUP
AND
H
OLD
T
IMES
W
ITH
R
ESPECT
TO
C
LOCK
R
ISING
E
DGE
Notes 9, 10 (ns)
LSH33-30
FTI = 0
FTI = 1
Setup Hold
Setup Hold
10
3
15
2
15
0
15
0
10
0
10
0
10
0
10
0
LSH33-20*
FTI = 0
FTI = 1
Setup Hold
Setup Hold
8
0
8
2
8
0
8
0
8
0
8
0
8
0
8
0
LSH33-40*
FTI = 0
FTI = 1
Setup Hold
Setup Hold
12
3
20
2
17
0
17
0
12
0
12
0
12
0
12
0
T
RI
-S
TATE
E
NABLE
/D
ISABLE
T
IMES
Notes 9, 10, 11 (ns)
LSH33-40*
LSH33-30
LSH33-20*
20
17
15
20
17
15
t
ENA
t
DIS
C
LOCK
C
YCLE
T
IME
AND
P
ULSE
W
IDTH
Notes 9, 10 (ns)
Minimum Cycle Time
Highgoing Pulse
Lowgoing Pulse
LSH33-40*
LSH33-30
LSH33-20*
30
20
15
12
9
7
12
9
7
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*D
ISCONTINUED
S
PEED
G
RADE