ChipFind - документация

Электронный компонент: LMU18JC35

Скачать:  PDF   ZIP
DEVICES INCORPORATED
LMU18
16 x 16-bit Parallel Multiplier
Multipliers
08/16/2000LDS.18-O
1
by the ENA and ENB controls. When
HIGH, these controls prevent appli-
cation of the clock to the respective
register. The TCA and TCB controls
specify the operands as two's com-
plement when HIGH, or unsigned
magnitude when LOW.
RND is loaded on the rising edge of CLK,
providing either ENA or ENB are LOW.
RND, when HIGH, adds `1' to the
most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.
At the output, the Right Shift control (RS)
selects either of two output formats. RS
LOW produces a 31-bit product with a
copy of the sign bit inserted in the MSB
postion of the least significant half. RS
HIGH gives a full 32-bit product. Two
16-bit output registers are provided to
hold the most and least significant
halves of the result (MSP and LSP) as
defined by RS. These registers are loaded
on the rising edge of CLK, subject to the
ENR control. When ENR is HIGH, clock-
ing of the result registers is prevented.
For asynchronous output these registers
may be made transparent by setting the
feed through control (FT) HIGH and
ENR LOW.
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP outputs to
be driven by the most significant half of
the result. MSPSEL HIGH routes the
least significant half of the result to the
MSP pins. The MSB of the result is avail-
able in both true and complemented
form to aid implementation of higher
precision multipliers.
u
u
u
u
u
35 ns Worst-Case Multiply Time
u
u
u
u
u Low Power CMOS Technology
u
u
u
u
u Full 32-bit Output Port --
No Multiplexing Required
u
u
u
u
u Two's Complement, Unsigned, or
Mixed Operands
u
u
u
u
u Three-State Outputs
u
u
u
u
u 84-pin PLCC, J-Lead
FEATURES
DESCRIPTION
LMU18
16 x 16-bit Parallel Multiplier
DEVICES INCORPORATED
The LMU18 is a high-speed, low
power 16-bit parallel multiplier.
The LMU18 is an 84-pin device
which provides simultaneous access
to all outputs.
The LMU18 produces the 32-bit
product of two 16-bit numbers.
Data present at the A inputs, along
with the TCA control bit, is loaded
into the A register on the rising edge
of CLK. B data and the TCB control
bit are similarly loaded. Loading of
the A and B registers is controlled
LMU18 B
LOCK
D
IAGRAM
A REGISTER
B REGISTER
REGISTER
RESULT
REGISTER
ENA
ENB
RND
FT
16
16
32
16
16
16
OEM
OEL
A
15-0
R
31-16
TCA
TCB
RS
ENR
FORMAT ADJUST
16
B
15-0
MSPSEL
CLK
R
31
R
15-0
DEVICES INCORPORATED
LMU18
16 x 16-bit Parallel Multiplier
Multipliers
08/16/2000LDS.18-O
2
F
IGURE
1
A
.
I
NPUT
F
ORMATS
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
15 14 13
2
1
0
2
0
(Sign)
2
1
2
2
2
13
2
14
2
15
15 14 13
2
1
0
2
0
(Sign)
2
1
2
2
2
13
2
14
2
15
Fractional Two's Complement (TCA, TCB = 1)
15 14 13
2
1
0
2
15
(Sign)
2
14
2
13
2
2
2
1
2
0
15 14 13
2
1
0
2
15
(Sign)
2
14
2
13
2
2
2
1
2
0
Integer Two's Complement (TCA, TCB = 1)
15 14 13
2
1
0
2
1
2
2
2
3
2
14
2
15
2
16
15 14 13
2
1
0
2
1
2
2
2
3
2
14
2
15
2
16
Unsigned Fractional (TCA, TCB = 0)
15 14 13
2
1
0
2
15
2
14
2
13
2
2
2
1
2
0
15 14 13
2
1
0
2
15
2
14
2
13
2
2
2
1
2
0
Unsigned Integer (TCA, TCB = 0)
A
IN
B
IN
MSP
LSP
31 30 29
18 17 16
2
0
(Sign)
2
1
2
2
2
13
2
14
2
15
15 14 13
2
1
0
2
0
(Sign)
2
16
2
17
2
28
2
29
2
30
Fractional Two's Complement (RS = 0)
31 30 29
18 17 16
2
31
(Sign)
2
30
2
29
2
18
2
17
2
16
15 14 13
2
1
0
2
15
2
14
2
13
2
2
2
1
2
0
Integer Two's Complement (RS = 1)
31 30 29
18 17 16
2
1
2
2
2
3
2
14
2
15
2
16
15 14 13
2
1
0
2
17
2
18
2
19
2
30
2
31
2
32
Unsigned Fractional (RS = 1)
31 30 29
18 17 16
2
31
2
30
2
29
2
18
2
17
2
16
15 14 13
2
1
0
2
15
2
14
2
13
2
2
2
1
2
0
Unsigned Integer (RS = 1)
31 30 29
18 17 16
2
1
(Sign)
2
0
2
1
2
12
2
13
2
14
15 14 13
2
1
0
2
15
2
16
2
17
2
28
2
29
2
30
Fractional Two's Complement (RS = 1)
DEVICES INCORPORATED
LMU18
16 x 16-bit Parallel Multiplier
Multipliers
08/16/2000LDS.18-O
3
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
OH
Output High Voltage
V
CC
= Min., I
OH
= 2.0 mA
2.4
V
V
OL
Output Low Voltage
V
CC
= Min., I
OL
= 8.0 mA
0.5
V
V
IH
Input High Voltage
2.0
V
CC
V
V
IL
Input Low Voltage
(Note 3)
0.0
0.8
V
I
IX
Input Current
Ground
V
IN
V
CC
(Note 12)
20
A
I
OZ
Output Leakage Current
Ground
V
OUT
V
CC
(Note 12)
20
A
I
CC1
V
CC
Current, Dynamic
(Notes 5, 6)
25
45
mA
I
CC2
V
CC
Current, Quiescent
(Note 7)
1.5
mA
Storage temperature ........................................................................................................... 65C to +150C
Operating ambient temperature ........................................................................................... 55C to +125C
V
CC
supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Mode
Temperature Range (Ambient)
Supply
Voltage
Active Operation, Commercial
0C to +70C
4.75 V
V
CC
5.25 V
Active Operation, Military
55C to +125C
4.50 V
V
CC
5.50 V
DEVICES INCORPORATED
LMU18
16 x 16-bit Parallel Multiplier
Multipliers
08/16/2000LDS.18-O
4
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
123456789012
LMU18
65*
45
35
20*
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
t
MC
Clocked Multiply Time
65
45
35
20
t
MUC
Unclocked Multiply Time
85
65
55
30
t
PW
Clock Pulse Width
15
15
15
9
t
S
Input Setup Time
15
15
12
11
t
H
Input Hold Time
5
5
5
1
t
D
Output Delay
30
30
28
18
t
SEL
Output Select Delay
25
25
25
18
t
ENA
Three-State Output Enable Delay (
Note 11
)
25
20
20
18
t
DIS
Three-State Output Disable Delay (
Note 11
)
24
20
20
18
SWITCHING CHARACTERISTICS
C
OMMERCIAL
O
PERATING
R
ANGE
(0C to +70C)
Notes 9, 10 (ns)
LMU18
75*
55*
45*
25*
Symbol
Parameter
Min
Max
Min
Max
Min
Max
t
MC
Clocked Multiply Time
75
55
45
25
t
MUC
Unclocked Multiply Time
95
85
65
38
t
PW
Clock Pulse Width
20
15
15
10
t
S
Input Setup Time
15
15
12
12
t
H
Input Hold Time
5
5
5
2
t
D
Output Delay
35
35
33
20
t
SEL
Output Select Delay
30
30
30
20
t
ENA
Three-State Output Enable Delay (
Note 11
)
25
20
20
20
t
DIS
Three-State Output Disable Delay (
Note 11
)
24
20
20
20
M
ILITARY
O
PERATING
R
ANGE
(55C to +125C)
Notes 9, 10 (ns)
S
WITCHING
W
AVEFORMS
HIGH IMPEDANCE
INPUT
t
ENA
t
DIS
t
PW
t
PW
t
MC
t
PW
t
H
t
S
CLOCK
OEM
OEL
R
31-0
t
D
t
MUC
t
SEL
MSPSEL
t
H
t
S
ENA, ENB
ENR
123456789012345678901234
123456789012345678901234
123456789012345678901234
*D
ISCONTINUED
S
PEED
G
RADE
DEVICES INCORPORATED
LMU18
16 x 16-bit Parallel Multiplier
Multipliers
08/16/2000LDS.18-O
5
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V
CC
will be clamped beginning at 0.6 V and
V
CC
+ 0.6 V. The device can withstand
indefinite operation with inputs in the
range of 0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
NCV F
4
2
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I
OH
and I
OL
at an output
voltage of V
OH
min and V
OL
max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of I
OH
and I
OL
respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 F ceramic capacitor should be
installed between V
CC
and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V
CC
and the tester common, and device
ground and tester common.
b. Ground and V
CC
supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and V
CC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the t
DIS
test,
the transition is measured to the
200mV level from the measured
steady-state output voltage with
10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V
1.5 V
3.5V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
V
OL
*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with I
OH
= 10mA and I
OL
= 10mA
Measured V
OH
with I
OH
= 10mA and I
OL
= 10mA
F
IGURE
B. T
HRESHOLD
L
EVELS
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT