DEVICES INCORPORATED

LMU112

12 x 12-bit Parallel Multiplier

Multipliers

08/16/2000LDS.112-K

25 ns Worst-Case Multiply Time

u Low Power CMOS Technology
u

u Replaces Fairchild MPY112K
u

u Two's Complement or Unsigned

Operands

u Three-State Outputs
u

u Package Styles Available:

· 48-pin PDIP
· 52-pin PLCC, J-Lead

FEATURES

DESCRIPTION

LMU112

12 x 12-bit Parallel Multiplier

DEVICES INCORPORATED

The LMU112 is a high-speed, low
power 12-bit parallel multiplier built
using advanced CMOS technology.
The LMU112 is pin and functionally
compatible with Fairchilds's MPY112K.

The A and B input operands are
loaded into their respective registers
on the rising edge of the separate
clock inputs (CLK A and CLK B).
Two's complement or unsigned
magnitude operands are accommo-
dated via the operand control bit (TC)

LMU112 B

LOCK

IAGRAM

A REGISTER

CLK A

CLK B

11-0

23-8

FORMAT ADJUST

B REGISTER

RESULT REGISTER

which is loaded along with the B
operands. The operands are specified
to be in two's complement format
when TC is asserted and unsigned
magnitude when TC is deasserted.
Mixed mode operation is not allowed.

For two's complement operands, the
17 most significant bits at the output
of the asynchronous multiplier array
are shifted one bit position to the left.
This is done to discard the redundant
copy of the sign-bit, which is in the
most significant bit position, and
extend the bit precision by one bit.
The result is then truncated to the 16
MSB's and loaded into the output
register on the rising edge of CLK B.

The contents of the output register are
made available via three-state buffers
by asserting OE. When OE is de-
asserted, the outputs (R

23-8

) are in the

high impedance state.

DEVICES INCORPORATED

LMU112

12 x 12-bit Parallel Multiplier

Multipliers

08/16/2000LDS.112-K

IGURE

NPUT

ORMATS

11 10 9

(Sign)

11 10 9

(Sign)

Fractional Two's Complement (TC = 1)

11 10 9

(Sign)

11 10 9

(Sign)

Integer Two's Complement (TC = 1)

11 10 9

Unsigned Fractional (TC = 0)

11 10 9

Unsigned Integer (TC = 0)

IGURE

UTPUT

ORMATS

23 22 21

14 13 12

(Sign)

11 10

Fractional Two's Complement

Integer Two's Complement

Unsigned Fractional

Unsigned Integer

MSP

LSP

23 22 21

14 13 12

(Sign)

11 10

23 22 21

14 13 12

11 10

23 22 21

14 13 12

11 10

DEVICES INCORPORATED

LMU112

12 x 12-bit Parallel Multiplier

Multipliers

08/16/2000LDS.112-K

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Output High Voltage

= Min., I

= 2.0 mA

2.4

Output Low Voltage

= Min., I

= 8.0 mA

0.5

Input High Voltage

2.0

Input Low Voltage

(Note 3)

0.0

0.8

Input Current

Ground

(Note 12)

µA

Output Leakage Current

Ground

OUT

(Note 12)

µA

CC1

Current, Dynamic

(Notes 5, 6)

CC2

Current, Quiescent

(Note 7)

1.0

Storage temperature ........................................................................................................... 65°C to +150°C

Operating ambient temperature ........................................................................................... 55°C to +125°C

supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V

Output current into low outputs ............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

AXIMUM

ATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

PERATING

ONDITIONS

To meet specified electrical and switching characteristics

LECTRICAL

HARACTERISTICS

Over Operating Conditions (Note 4)

Mode

Temperature Range (Ambient)

Supply

Voltage

Active Operation, Commercial

0°C to +70°C

4.75 V

5.25 V

Active Operation, Military

55°C to +125°C

4.50 V

5.50 V

DEVICES INCORPORATED

LMU112

12 x 12-bit Parallel Multiplier

Multipliers

08/16/2000LDS.112-K

123456789012

1234567890123456789012345678901212

LMU112

60*

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Clocked Multiply Time

Clock Pulse Width

Input Register Setup Time

Input Register Hold Time

Output Delay

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

OMMERCIAL

PERATING

ANGE

(0°C to +70°C)

Notes 9, 10 (ns)

WITCHING

AVEFORMS

LMU112

65*

55*

30*

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Clocked Multiply Time

Clock Pulse Width

Input Register Setup Time

Input Register Hold Time

Output Delay

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

ILITARY

PERATING

ANGE

(55°C to +125°C)

Notes 9, 10 (ns)

SWITCHING CHARACTERISTICS

HIGH IMPEDANCE

INPUT

ENA

DIS

CLK A

CLK B

23-8

123456789012345678901234

ISCONTINUED

PEED

RADE

DEVICES INCORPORATED

LMU112

12 x 12-bit Parallel Multiplier

Multipliers

08/16/2000LDS.112-K

1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.

2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.

3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V

will be clamped beginning at 0.6 V and
V

+ 0.6 V. The device can withstand

indefinite operation with inputs in the
range of 0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.

4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.

5. Supply current for a given applica-
tion can be accurately approximated by:

where

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.

7. Tested with all inputs within 0.1 V of
V

or Ground, no load.

8. These parameters are guaranteed
but not 100% tested.

NCV F

NOTES

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t

DIS

test), and input levels of nominally

0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I

and I

at an output

voltage of V

min and V

max

respectively. Alternatively, a diode
bridge with upper and lower current
sources of I

and I

respectively,

and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.

This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

a. A 0.1 µF ceramic capacitor should be
installed between V

and Ground

leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V

and the tester common, and device
ground and tester common.

b. Ground and V

supply planes

must be brought directly to the DUT
socket or contactor fingers.

c. Input voltages should be adjusted to
compensate for inductive ground and V

noise to maintain required DUT input
levels relative to the DUT ground pin.

10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.

11. For the t

ENA

test, the transition is

measured to the 1.5 V crossing point
with datasheet loads. For the t

DIS

test,

the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V

, is set at 3.5 V for Z-to-0

and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.

12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V

3.5V Vth

1.5 V

0V Vth

Measured V

with I

= 10mA and I

= 10mA

Measured V

with I

= 10mA and I

= 10mA

IGURE

B. T

HRESHOLD

EVELS

IGURE

A. O

UTPUT

OADING

IRCUIT

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