DEVICES INCORPORATED
LF2249
12 x 12-bit Digital Mixer
Video Imaging Products
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08/16/2000LDS.2249-J
1
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40 MHz Data and Computation Rate
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Two 12 x 12-bit Multipliers with
Individual Data Inputs
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Separate 16-bit Input Port for
Cascading Devices
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Independent, User-Selectable 116
Clock Pipeline Delay for Each Data
Input
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User-Selectable Rounding of Products
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Fully Registered, Pipelined
Architecture
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Three-State Outputs
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Fully TTL Compatible
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Replaces TRW/Raytheon/Fairchild
TMC2249
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u 120-pin PQFP
The LF2249 is a high-speed digital
mixer comprised of two 12-bit
multipliers and a 24-bit accumulator.
All multiplier inputs are user acces-
sible, and each can be updated on
every clock cycle. The LF2249 utilizes
a pipelined architecture with fully
registered inputs and outputs and an
asynchronous three-state output
enable control for optimum flexibility.
Independent input register clock
enables allow the user to hold the
data inputs over multiple clock cycles.
Each multiplier input also includes a
user-selectable 1-16 clock pipeline
delay. The output of each multiplier
can be independently negated under
NEG
1
S
15-0
16
RND
FT
CAS
15-0
CASEN
SWAP
OE
4
4
3
2 : 1
24
16
2 : 1
2 : 1
16
2's COMP
116
116
ADEL
3-0
A
11-0
ENA
BDEL
3-0
B
11-0
ENB
2's COMP
116
116
CDEL
3-0
C
11-0
ENC
DDEL
3-0
D
11-0
END
4
4
NEG
2
ACC
CLK
NOTE: NUMBERS IN REGISTERS INDICATED
NUMBER OF PIPELINE DELAYS.
16
1
0
0
1
16
MS
LS
FEATURES
DESCRIPTION
LF2249
12 x 12-bit Digital Mixer
user control for subtraction of prod-
ucts. The sum of the products can
also be internally rounded to 16 bits
during the accumulation process.
A separate 16-bit input port con-
nected to the accumulator is included
to allow cascading of multiple
LF2249s. Access to all 24 bits of the
accumulator is gained by switching
between upper or lower 16-bit words.
The accumulated output data is
updated on every clock cycle.
All inputs and outputs of the LF2249
are registered on the rising edge of
clock, except for OE. Internal pipeline
registers for all data and control
inputs are provided to maintain
DEVICES INCORPORATED
LF2249 B
LOCK
D
IAGRAM
DEVICES INCORPORATED
LF2249
12 x 12-bit Digital Mixer
Video Imaging Products
08/16/2000LDS.2249-J
2
synchronous operation between the
incoming data and all available
control functions. The LF2249 oper-
ates at a clock rate of 40 MHz over the
full commercial temperature and
supply voltage ranges.
Because of its flexibility, the LF2249 is
ideally suited for applications such as
image switching and mixing, digital
quadrature mixing and modulating,
FIR filtering, and arithmetic function
and waveform synthesis.
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK -- Master Clock
The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.
Inputs
A
11-0
D
11-0
-- Data Inputs
A
11-0
D
11-0
are 12-bit data input regis-
ters. Data is latched into the input reg-
isters on the rising edge of CLK. The
contents of the input registers are
clocked into the top of the correspond-
ing 16-stage pipeline delay (pushing the
contents of the register stack down one
register position) on the next clock cycle
if the pipeline register stack is enabled.
The LSBs are A
0
-D
0
(Figure 1a).
CAS
15-0
-- Cascade Data Input
CAS
15-0
is the 16-bit cascade data input
port. Data is latched into the register on
the rising edge of CLK. The LSB is CAS
0
(Figure 1a).
ADEL
3-0
A
11-0
ENA
16 : 1
4
12
12
CLK
R
1
R
2
R
16
D
ETAILED
V
IEW
OF
B
LOCK
D
IAGRAM
O
UTLINED
A
REA
10
9
8
11
7
6
5
4
3
2
1
0
2
10
2
9
2
8
2
11
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
(Sign)
15 14 13
10
9
8
12 11
7
6
5
4
3
2
1
0
2
23
2
22
2
21
2
18
2
17
2
16
2
20
2
19
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
(Sign)
F
IGURE
1
A
.
I
NPUT
F
ORMATS
15 14 13
10
9
8
12 11
7
6
5
4
3
2
1
0
2
23
2
22
2
21
2
18
2
17
2
16
2
20
2
19
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
(Sign)
15 14 13
10
9
8
12 11
7
6
5
4
3
2
1
0
2
15
2
14
2
13
2
10
2
9
2
8
2
12
2
11
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
Cascade Input
Data Input
Sum Output (Upper 16 bits)
Sum Output (Lower 16 bits)
DEVICES INCORPORATED
LF2249
12 x 12-bit Digital Mixer
Video Imaging Products
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08/16/2000LDS.2249-J
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ACC -- Accumulator Control
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging products are
added to the sum of the previous prod-
ucts.
RND -- Rounding Control
When RND is HIGH, the sum of the
products of the data being input on
the current clock cycle will be
rounded to 16 bits. To avoid the accu-
mulation of roundoff errors, round-
ing is only performed during the first
cycle of each accumulation process.
SWAP -- Output Select
The SWAP control allows the user to
access all 24 bits of the accumulator
output by switching between upper
and lower 16-bit words. When SWAP
is HIGH, the upper 16 bits of the accu-
mulator are always output. When
SWAP is LOW, the lower 16 bits of the
accumulator are output on every
other clock cycle. As long as SWAP
remains LOW, new output data will
not be clocked into the output regis-
ters.
OE -- Output Enable
When the OE signal is LOW, the
current data in the output registers
is available on the S
15-0
pins. When
OE is HIGH, the outputs are in a
high-impedance state.
Outputs
S
15-0
-- Data Output
The current 16-bit result is available
on the S
15-0
outputs. The output data
may be either the upper or lower 16
bits of the accumulator output, de-
pending on the state of SWAP. The
LSB is S
0
(Figure 1b).
Controls
ENAEND -- Pipeline Register Enable
Input data in the
N
(
N
= A, B, C, or D)
input register is latched into the corre-
sponding pipeline register stack on
each rising edge of CLK for which EN
N
is LOW. Data already in the
N
register
stack is pushed down one register posi-
tion. When EN
N
is HIGH, the data in
the
N
pipeline register stack does not
change, and the data in the
N
input
register will not be stored in the register
stack.
ADEL
3-0
DDEL
3-0
-- Pipeline Delay
Select
N
DEL (
N
= A, B, C, or D) is the 4-bit
registered pipeline delay select word.
N
DEL determines which stage of the
N
pipeline register stack is routed to the
multiplier inputs. The minimum delay
is one clock cycle (
N
DEL = 0000), and
the maximum delay is 16 clock cycle
(
N
DEL = 1111). Upon power up, the
values of ADELDDEL and the con-
tents of the pipeline register stacks are
unknown and must be initialized by the
user.
NEG
1
NEG
2
-- Negate Control
The NEG
1
and NEG
2
controls deter-
mine whether a subtraction or accumu-
lation of products is performed. When
NEG
1
is HIGH, the product A x B is
negated, causing the product to be sub-
tracted from the accumulator contents.
Likewise, when NEG
2
is HIGH, the
product C x D is negated, causing the
product to be subtracted as well. NEG
1
and NEG
2
determine the operation to
be performed on the data input during
the current clock cycle when ADEL
DDEL = 0000.
CASEN -- Cascade Enable
When CASEN is LOW, data being in-
put on the CAS
15-0
inputs during that
clock cycle will be registered and accu-
mulated internally. When CASEN is
HIGH, the CAS
15-0
inputs are ignored.
FT -- Feedthrough Control
When FT is LOW and ADELDDEL =
0000, data being input on the CAS
15-0
inputs is delayed three clock cycles to
align the data with the data being input
on the A
11-0
D
11-0
inputs. When FT is
HIGH, the cascade data being input is
routed around the three delay registers
to simplify the cascading of multiple
devices.
DEVICES INCORPORATED
LF2249
12 x 12-bit Digital Mixer
Video Imaging Products
08/16/2000LDS.2249-J
4
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
OH
Output High Voltage
Vcc = Min., I
OH
= 2.0 mA
2.4
V
V
OL
Output Low Voltage
Vcc = Min., I
OL
= 4.0 mA
0.4
V
V
IH
Input High Voltage
2.0
V
CC
V
V
IL
Input Low Voltage
(Note 3)
0.0
0.8
V
I
IX
Input Current
Ground
V
IN
V
CC
(Note 12)
10
A
I
OZ
Output Leakage Current
(Note 12)
40
A
I
CC1
V
CC
Current, Dynamic
(Notes 5, 6)
100
mA
I
CC2
V
CC
Current, Quiescent
(Note 7)
6
mA
C
IN
Input Capacitance
T
A
= 25C, f = 1 MHz
10
pF
C
OUT
Output Capacitance
T
A
= 25C, f = 1 MHz
10
pF
Storage temperature ........................................................................................................... 65C to +150C
Operating ambient temperature ........................................................................................... 55C to +125C
V
CC
supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... 0.5 V to V
CC
+ 0.5 V
Signal applied to high impedance output ...................................................................... 0.5 V to V
CC
+ 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Mode
Temperature Range (Ambient)
Supply
Voltage
Active Operation, Commercial
0C to +70C
4.75 V
V
CC
5.25 V
Active Operation, Military
55C to +125C
4.50 V
V
CC
5.50 V
DEVICES INCORPORATED
LF2249
12 x 12-bit Digital Mixer
Video Imaging Products
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08/16/2000LDS.2249-J
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LF2249-
40*
33
25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
t
CYC
Cycle Time
40
33
25
t
PWL
Clock Pulse Width, LOW
15
15
10
t
PWH
Clock Pulse Width, HIGH
10
10
10
t
S
Input Setup Time
8
8
7
t
H
Input Hold Time
0
0
0
t
D
Output Delay
17
15
14
t
ENA
Three-State Output Enable Delay
(Note 11)
15
15
15
t
DIS
Three-State Output Disable Delay
(Note 11)
15
15
15
SWITCHING CHARACTERISTICS
C
OMMERCIAL
O
PERATING
R
ANGE
(0C to +70C)
Notes 9, 10 (ns)
LF2249-
40*
33*
Symbol
Parameter
Min
Max
Min
Max
t
CYC
Cycle Time
40
33
t
PWL
Clock Pulse Width, LOW
15
15
t
PWH
Clock Pulse Width, HIGH
10
10
t
S
Input Setup Time
8
8
t
H
Input Hold Time
0
0
t
D
Output Delay
17
15
t
ENA
Three-State Output Enable Delay
(Note 11)
15
15
t
DIS
Three-State Output Disable Delay
(Note 11)
15
15
M
ILITARY
O
PERATING
R
ANGE
(55C to +125C)
Notes 9, 10 (ns)
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*D
ISCONTINUED
S
PEED
G
RADE
CLK
t
H
t
DIS
A
11-0
D
11-0
CONTROLS
(Except OE)
S
15-0
*
N
t
S
N + 1
t
ENA
HIGH IMPEDANCE
t
PWH
t
PWL
t
D
S
N
S
N + 1
S
N + 2
1
2
3
6
7
8
OE
N + 2
*Assumes ADELDDEL = 0000
S
WITCHING
W
AVEFORMS
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