DEVICES INCORPORATED

LF2246

11 x 10-bit Image Filter

Video Imaging Products

08/16/2000LDS.2246-K

2-11

66 MHz Data and Coefficient Input
and Computation Rate

u Four 11 x 10-bit Multipliers with

Individual Data and Coefficient
Inputs and a 25-bit Accumulator

u User-Selectable Fractional or

Integer Two's Complement Data
Formats

u Fully Registered, Pipelined Archi-

tecture

u Input and Output Data Registers,

with User-Configurable Enables

u Three-State Outputs
u

u Fully TTL Compatible
u

u Ideally Suited for Image Processing

and Filtering Applications

u Replaces TRW/Raytheon/Fairchild

TMC2246

u 120-pin PQFPP

FEATURES

DESCRIPTION

LF2246

11 x 10-bit Image Filter

DEVICES INCORPORATED

The LF2246 consists of an array of
four 11 x 10-bit registered multipliers
followed by a summer and a 25-bit
accumulator. All multiplier inputs
are user accessible and can be up-
dated every clock cycle with either
fractional or integer two's comple-
ment data. The pipelined architecture
has fully registered input and output
ports and an asynchronous three-state
output enable control to simplify the
design of complex systems. The
pipeline latency for all inputs is five
clock cycles.

Storage for mixing and filtering
coefficients can be accomplished by
holding the data or coefficient inputs
over multiple clock cycles. A 25-bit
accumulator path allows cumulative
word growth which may be internally
rounded to 16 bits. Output data is
updated every clock cycle and may be
held under user control. All inputs,

outputs, and controls are registered
on the rising edge of clock, except for
OEN. The LF2246 operates at a clock
rate of 66 MHz over the full tempera-
ture and supply voltage ranges.

The LF2246 is applicable for perform-
ing pixel interpolation in image
manipulation and filtering applica-
tions. The LF2246 can perform a
bilinear interpolation of an image (4-
pixel kernels) at real-time video rates
when used with an image resampling
sequencer. Larger kernels or more
complex functions can be realized by
utilizing multiple devices.

Unrestricted access to all data and
coefficient input ports provides the
LF2246 with considerable flexibility in
applications such as digital filters,
adaptive FIR filters, mixers, and other
similar systems requiring high-speed
processing.

LF2246 B

LOCK

IAGRAM

100

ENB1

100

ENB2

OCEN

ACC

FSEL

CLK

OEN

TO ALL REGISTERS

150

ENSEL

100

ENB3

100

ENB4

DEVICES INCORPORATED

LF2246

11 x 10-bit Image Filter

Video Imaging Products

2-12

08/16/2000LDS.2246-K

IGURE

NPUT

ORMATS

INPUT REGISTER

ENB1-4

ENSEL

HELD

Data `

Coefficient `

None

X = "Don't Care"
`

' = 1, 2, 3, or 4

ABLE

NPUT

EGISTER

ONTROL

SIGNAL DEFINITIONS

Power

and GND

+5 V power supply. All pins must be
connected.

Clock

CLK -- Master Clock

The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.

Inputs

90

D4

90

-- Data Input

D1D4 are 10-bit data input registers.
The LSB is D

(Figure 1a).

100

C4

100

-- Coefficient Input

C1C4 are 11-bit coefficient input regis-
ters. The LSB is C

(Figure 1a).

Outputs

150

-- Data Output

The current 16-bit result is available on
the S

150

outputs (Figure 1b).

OCEN -- Clock Enable

When OCEN is LOW, data in the pre-
mux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register is
held preventing the output register's
contents from changing (if FSEL does
not change). Accumulation continues
internally as long as ACC is HIGH,
despite the state of OCEN.

FSEL -- Format Select

When the FSEL input is LOW, the data
input during the current clock cycle is
assumed to be in fractional two's
complement format, and the upper 16
bits of the accumulator are presented at
the output. Rounding of the accumula-
tor result to 16 bits is performed if the
accumulator control input ACC is
LOW. When FSEL is HIGH, the data
input is assumed to be in integer two's
complement format, and the lower 16
bits of the accumulator are presented at
the output. No rounding is performed
when FSEL is HIGH.

ACC -- Accumulator Control

The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. If FSEL is also LOW,
one-half LSB rounding to 16 bits is per-
formed on the result. This allows sum-
mations without propagating roundoff
errors. When ACC is HIGH, the emerg-
ing product is added to the sum of the
previous products, without additional
rounding.

IGURE

UTPUT

ORMATS

15 14 13

12 11

(Sign)

Fractional Two's Complement (FSEL = 0)

15 14 13

12 11

(Sign)

Integer Two's Complement (FSEL = 1)

Data

(Sign)

Integer Two's Complement (FSEL = 1)

(Sign)

Fractional Two's Complement (FSEL = 0)

Coefficient

Controls

ENB1ENB4 -- Input Enable

The ENB

(

= 1, 2, 3, or 4) input allows

either or both the D

and C

registers to

be updated on each clock cycle. When
ENB

is LOW, registers D

and C

are

both strobed by the next rising edge of
CLK. When ENB

is HIGH and ENSEL

is LOW, register D

is strobed while

is held. If both ENB

and

ENSEL are HIGH, register D

is held,

and register C

is strobed (Table 1).

ENSEL -- Enable Select

The ENSEL input in conjunction with
the individual input enables ENB1
ENB4 determines whether the data or
the coefficient input registers will be
held on the next rising edge of CLK
(Table 1).

OEN -- Output Enable

When the OEN signal is LOW, the cur-
rent data in the output register is avail-
able on the S

150

pins. When OEN is

HIGH, the outputs are in a high-imped-
ance state.

DEVICES INCORPORATED

LF2246

11 x 10-bit Image Filter

Video Imaging Products

08/16/2000LDS.2246-K

2-13

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Output High Voltage

= Min., I

= 2.0 mA

2.4

Output Low Voltage

= Min., I

= 4.0 mA

0.4

Input High Voltage

2.0

Input Low Voltage

(Note 3)

0.0

0.8

Input Current

Ground

(Note 12)

µA

Output Leakage Current

(Note 12)

µA

CC1

Current, Dynamic

(Notes 5, 6)

100

CC2

Current, Quiescent

(Note 7)

Input Capacitance

= 25°C, f = 1 MHz

OUT

Output Capacitance

= 25°C, f = 1 MHz

Storage temperature ........................................................................................................... 65°C to +150°C

Operating ambient temperature ........................................................................................... 55°C to +125°C

supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V

Input signal with respect to ground ............................................................................... 0.5 V to V

+ 0.5 V

Signal applied to high impedance output ...................................................................... 0.5 V to V

+ 0.5 V

Output current into low outputs ............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

AXIMUM

ATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

PERATING

ONDITIONS

To meet specified electrical and switching characteristics

LECTRICAL

HARACTERISTICS

Over Operating Conditions (Note 4)

Mode

Temperature Range (Ambient)

Supply

Voltage

Active Operation, Commercial

0°C to +70°C

4.75 V

5.25 V

Active Operation, Military

55°C to +125°C

4.50 V

5.50 V

DEVICES INCORPORATED

LF2246

11 x 10-bit Image Filter

Video Imaging Products

2-14

08/16/2000LDS.2246-K

1234567890123456789012345678901212345678901234567

123456789012345678901234

LF2246

33*

Symbol

Parameter

Min

Max

Min

Max

Min

Max

CYC

Cycle Time

PWL

Clock Pulse Width Low

PWH

Clock Pulse Width High

Input Setup Time

Input Hold Time

Output Delay

DIS

Three-State Output Disable Delay

(Note 11)

ENA

Three-State Output Enable Delay

(Note 11)

SWITCHING CHARACTERISTICS

OMMERCIAL

PERATING

ANGE

(0°C to +70°C)

Notes 9, 10 (ns)

LF2246

33*

25*

Symbol

Parameter

Min

Max

Min

Max

CYC

Cycle Time

PWL

Clock Pulse Width Low

PWH

Clock Pulse Width High

Input Setup Time

Input Hold Time

Output Delay

DIS

Three-State Output Disable Delay

(Note 11)

ENA

Three-State Output Enable Delay

(Note 11)

ILITARY

PERATING

ANGE

(55°C to +125°C)

Notes 9, 10 (ns)

123456789012345678901234

ISCONTINUED

PEED

RADE

WITCHING

AVEFORMS

CLK

DIS

9-0

10-0

OEN

15-0

N+1

ENA

HIGH IMPEDANCE

PWH

PWL

N+1

CONTROLS

(Except OEN)

DEVICES INCORPORATED

LF2246

11 x 10-bit Image Filter

Video Imaging Products

08/16/2000LDS.2246-K

2-15

1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.

2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.

3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V

will be clamped beginning at 0.6 V and
V

+ 0.6 V. The device can withstand

indefinite operation with inputs in the
range of 0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.

4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.

5. Supply current for a given applica-
tion can be accurately approximated by:

where

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

6. Tested with all outputs changing ev-
ery cycle and no load, at a 30 MHz clock
rate.

7. Tested with all inputs within 0.1 V of
V

or Ground, no load.

8. These parameters are guaranteed
but not 100% tested.

NCV F

NOTES

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t

DIS

test), and input levels of nominally

0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I

and I

at an output

voltage of V

min and V

max

respectively. Alternatively, a diode
bridge with upper and lower current
sources of I

and I

respectively,

and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.

This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

a. A 0.1 µF ceramic capacitor should be
installed between V

and Ground

leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V

and the tester common, and device
ground and tester common.

b. Ground and V

supply planes

must be brought directly to the DUT
socket or contactor fingers.

c. Input voltages should be adjusted to
compensate for inductive ground and V

noise to maintain required DUT input
levels relative to the DUT ground pin.

10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.

11. For the t

ENA

test, the transition is

measured to the 1.5 V crossing point
with datasheet loads. For the t

DIS

test,

the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V

, is set at 3.5 V for Z-to-0

and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.

12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V

3.5V Vth

1.5 V

0V Vth

Measured V

with I

= 10mA and I

= 10mA

Measured V

with I

= 10mA and I

= 10mA

IGURE

B. T

HRESHOLD

EVELS

IGURE

A. O

UTPUT

OADING

IRCUIT

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