Command Interface 4M-Bit Ma
ROM with Expansion I/O
HF88M04
Preliminary Product Specification
Product Name
Command Interface 4M-Bit Mask ROM with Expansion I/O
KB Doc. No.
HF88M04.DOC
KB Product. No.
HF88M04
- Table of Contents
1 Function
Description ............................................................................................2
2 Features.................................................................................................................2
3
Functional block diagram ....................................................................................3
Pin Description..............................................................................................................4
4.1 Pad
Location.............................................................................................5
4.2 Pad
Coordination.....................................................................................6
5 Device
Operation...................................................................................................7
5.1
Retrieve data in Data File........................................................................9
5.2
Loading the Address Counter.................................................................9
5.3
Sequential Read Mode and Auto Increment of Address Counter.....10
5.4
Output data to External I/O..................................................................10
5.5
Reading Input pin status .......................................................................10
5.6
Retrieving the Contents of Expansion I/O registers ........................... 11
6 Timing
Diagrams ................................................................................................ 11
6.1
Data File Read Cycle ............................................................................. 11
6.2
Interrupted by I/O when Loading Address Counter.......................... 11
6.3
Setting and Reading the I/O Mode for P0 and P1...............................12
6.4
Reading P0 and P1 in Mixed-I/O Mode...............................................12
6.5
Reading the input pins...........................................................................13
6.6
Output to P0 and P1 ..............................................................................13
7
Absolute Maximum Rating.................................................................................14
8
AC Electrical Characteristics .............................................................................14
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Command Interface 4M-Bit Ma
ROM with Expansion I/O
HF88M04
9
DC Electrical Characteristics .............................................................................15
10 Application
Circuit
Diagram ..........................................................................15
1 Function Description
The HF88M04 is a command interfaced 512K x 8 bit Mask ROM. It features
command mode interface with external CPU or MCU. In other words, it uses only
8-bit data bus and a few additional control pins to load addresses and provide the
ROM access as well as expansion I/O ports capability. This design not only reduces
pin count required to access data in ROM dramatically but also allows for systems
expansion to higher capacity memories while using the existing board design. The
application areas include voice, graphic, data storage in consumer product.
2 Features
Data File Mode with only 11 pin interface
Sixteen-bit Expansion I/O pins with three-state mode
Voltage range 2.4V ~ 5.5V
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Command Interface 4M-Bit Ma
ROM with Expansion I/O
HF88M04
Organization
- Memory Cell Array: 512K x 8
Sequential Read Operation in Data File Operation Mode
- Sequential Access : 120ns (min.) at V
DD
= 5.0V
Command/Address/Data Multiplexed I/O port
Low Operation Current (Typical)
- 10
A Standby mode Current
- 10mA Active Read Current
Package bare chip, PLCC32
3 Functional block diagram
MEMORY
CELL
ARRAY
SENSE
AMP.
OEn
X BUFFER &
DECODER
[D7.. D0]
CONTROL
LOGIC
Y BUFFER &
DECODER
CEn
[P00..P07]
[P10..P17]
[AC18..A0]
AC0
AC1
AC2
P0
DIR0
P1
DIR1
WEn
RS2..RS0
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Command Interface 4M-Bit Ma
ROM with Expansion I/O
HF88M04
4 Pin Description
HF88M04-PLCC32
11
2
9
8
7
6
5
4
29
28
24
27
3
30
31
2
23
25
13
14 15
18 19 20
21
22
32
16
1
12
17
26
P01
P02
P03
P04
P05
P06
P07
P14
P16
P15
OE
P10
P17
RS
1
RS
2
RS
0
P12
P13
D0
D1 D2
D4 D5 D6
D7
CE
VD
D
VSS
WE
P00
D3
P11
Symbol Pin
No. I/O
Description
VDD
32
P Positive power supply input pin.
VSS 16
P
Gound
pin.
CEn
22
I The CEn (Chip Enable) input is the device selection and
power control for internal Mask ROM array. Whenever
CEn goes high, the internal Mask ROM will enter standby
(power saving) mode and accesses to internal registers are
inhibited. Otherwise, it is in active mode and the
contents of the ROM and registers can be accessed.
Please note that only accesses to the internal registers are
inhibited, but the status of I/O registers are not affected by
the CEn pin and will remain unchanged. CEn is also
useful to uniquely select a certain device for applications
where multiple-chip array is required.
WEn
1
I WEn controls writing to internal registers such as the
Output Port Registers, Direction Registers, Address
Counter and Data on D7 ~ D0 are latched on the rising
edge of the WE pulse. The WEn (Write Enable) input is
internally pulled-up to VDD to prevent pin floating. So
this pin should stay at `1' state when inactive to prevent
unintended current consumption.
OEn
24
I OEn (Output Enable) is the output control which gates
ROM array data, expansion I/O ports, Direction Registers
to the data I/O pins D7 ~ D0. The internal Address
Counter will automatically increment by one with each
rising edge of OEn pin in Sequentially Read mode.
RS2~RS0
I Register Select pins RS2 ~ RS0 for accessing ROM data,
Address Counter, as well as expansion I/O ports.
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Command Interface 4M-Bit Ma
ROM with Expansion I/O
HF88M04
P17 ~ P10
I/O Bi-directional I/O port P1.
P07 ~ P00
I/O Bi-directional I/O port P0.
D7 ~ D0
21 ~ 17,
15 ~13
IO The Bi-directional Data I/O pins are used to input Starting
Address, setting the Expansion I/O direction and Output
Registers, and to output ROM array data during read
operations, contents of I/O Registers and status of input
pins. The D7 ~ D7 float to high-impedance when the chip
is deselected (CEn high) or when the outputs are disabled.
4.1 Pad
Location
P16
P15
P10
P11
P13
P12
D7
D6
D5
D4
D3
D2
D1
D0
P00
P01
P02
P03
NC
NC
NC
NC
P04
P05
P06
P07
P14
P17
WEN
VDD
VDD
VDD
RS2
RS1
RS0
OEN
CEN
VSS
VSS
VSS
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