King Billion Electronics Co., Ltd

HE84770C

HE80000 SERIES

August 25, 2003

Page 1 of 25

V1.1E

This specification is subject to change without notice. Please contact sales person for the latest version before use.

- Table of Contents -

General Description ___________________________________________________________________2

Features _____________________________________________________________________________2

Functional Block Diagram______________________________________________________________3

Pin Description _______________________________________________________________________3

LCD RAM Map ______________________________________________________________________5

LCD Power Supply____________________________________________________________________8

6.1.

LCDC Control register _____________________________________________________________10

Oscillators __________________________________________________________________________10

General Purpose I/O__________________________________________________________________12

Key Scan Circuit_____________________________________________________________________13

10.

Timer1 ___________________________________________________________________________15

11.

Timer2 ___________________________________________________________________________16

12.

Time Base Interrupt________________________________________________________________18

13.

Watch Dog Timer __________________________________________________________________18

14.

Digital-to-Analog Converter _________________________________________________________19

15.

Pulse-Width Modulation ____________________________________________________________20

16.

Absolute Maximum Rating __________________________________________________________21

17.

Recommended Operating Conditions _________________________________________________21

18.

AC/DC Characteristics _____________________________________________________________21

19.

Application Circuit_________________________________________________________________23

20.

Important Note ____________________________________________________________________24

21.

Updated Record ___________________________________________________________________25

King Billion Electronics Co., Ltd

HE84770C

HE80000 SERIES

August 25, 2003

Page 2 of 25

V1.1E

This specification is subject to change without notice. Please contact sales person for the latest version before use.

1. General Description

HE84770C is a member of 8-bit Micro-controller series developed by King Billion Electronics. Four
LCD driver configurations, 32 COM x 128 SEG, 48 COM x 112 SEG, 64 COM x 96 SEG or 80 COM x
80 SEG are available by mask option. 24 LCD segment driver pins are multiplexed with I/O pins to
provide flexibility of wide variety of combinations to suit the needs of applications. The built-in LCD
power supply is equipped with voltage charge-pump circuit to generate the high voltage required by the
high duty LCD driver, bias voltage generating circuit and input voltage regulator circuit to supply stable
LCD display effect over the wide battery life. The built-in OP comparator can be used with (light, voice,
temperature, humility) sensor and used as battery low detection. 7-bit current-type D/A converter and
PWM device provide the complete speech output mechanism. The 2 MB ROM can be used in the storage
of speech, graphic, text, etc. It is ideal for applications such as Translator, Data Bank, Educational Toy,
Digital Voice Recording System, etc.

The instruction set of HE80000 series is easy to learn and simple to use. Only 32 instructions with four
addressing modes are provided. Most of instructions take only 3 oscillator clocks to execute. The
processing power is enough to most of battery operation system.

2. Features

Operation Voltage:

2.4V ~ 3.6V

System Clock:

DC ~ 8MHz @ 3.6V

DC ~ 4MHz @ 2.4V

Internal ROM:

2 MB (256 KB Program ROM + 1792 KB Data ROM)

Internal RAM:

16 KB

Dual Clock System: Fast clock:

32768 ~ 8M Hz (No Internal Clock)

Slow clock: 32768 Hz

Operation Mode:

Fast, Slow, Idle and Sleep modes.

24 ~ 48 bit bi-directional general purpose I/O port with push-pull or Open-Drain output type

selectable for each I/O pin by mask option. 24 of them are multiplexed with LCD segment
pins.

Built-in 4x20 hardware keyboard scan circuit (multiplexed with LCD SEG pin) helps to

reduce the pin counts as well as the firmware effort.

Voltage Detector with two detecting thresholds.
Four LCD configurations: 32 COM x 128 SEG, 48 COM x 112 SEG, 64 COM x 96 SEG or

80 COM x 80 SEG. All of LCD configurations are B TYPE.

Built-in LCD power supply with input voltage regulator, x3, x4, x5 voltage multiplier and

bias voltage generating circuit.

One 7-bit current-type DAC output.
Single-ended Pulse Width Modulation circuit for alternative voice output.
Built-in OP comparator.
Two 16-bit timers and one Time-Base timer.
Watch Dog Timer to prevent deadlock condition.
Two external interrupts and three internal timer interrupts.
Instruction set: 32 instructions with 4 addressing mode.

King Billion Electronics Co., Ltd

HE84770C

HE80000 SERIES

August 25, 2003

Page 3 of 25

V1.1E

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3. Functional Block Diagram

SEG

FXI, FXO

COM

LCD

Driver

8 Bit CPU

Fast Clock

OSC.

2 MB ROM

SXI, SXO

LCD Power

Supply

Slow Clock

OSC

16 KB RAM

PRTC, PRTD, PRT10,

PWM

PRT17

I/O Port

TC1

PWM

SGKY[43..24]

TC2

VO, DAO

Key Scan

DAC

TBI

OPO,OPIN, OPIP

WDT

OP Amp

4. Pin Description

HE84770

1
2

4
5

7
8

12
13

15
16

18
19

20
21

23
24

26
27

30 31

32 33 34

35 36 37

38 39 40

41 42

43 44 45

46 47 48

49 50 51

52 53

54 55 56

57 58 59

60 61 62

63 64

65 66 67

68 69 70

71 72 73

74 75 76

77 78

79 80 81

82 83 84

85 86 87

88 89

90 91 92

93 94 95

96 97 98

99 100

101 102 103

104 105 106

107 108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

SEG48
SEG47

SEG46

SEG45
SEG44

SGKY43

SGKY42
SGKY41

SGKY40
SGKY39

SGKY38

SGKY37
SGKY36

SGKY35

SGKY34
SGKY33

SGKY32

SGKY31
SGKY30

SGKY29
SGKY28

SGKY27

SGKY26
SGKY25

SGKY24

PRT147
PRT146

PRT145
PRT144

1
43

1
42

1
41

1
40

1
57

1
56

1
55

1
54

1
53

1
52

1
51

1
50

1
77

1
76

1
75

1
74

1
73

1
72

1
71

1
70

LVL1 LVL2 LVL3

LVL4 LVL5 LG

LVP LC

AP4A

AP2B

AP2A

AP1A

AP1B

AP3A

LVR

LVAG GN

VO DA

I
N

I
P

_
N

SXO

SXI

VDD

PRT107

PRT106

PRT105

PRT104

PRT103

PRT102

PRT101

PRT100

PRTD7

PRTD6

PRTD5

PRTD4

PRTD3

PRTD2

PRTD1

PRTD0

GND_PWM

PWM

PRTC7

PRTC6

PRTC5

PRTC4

PRTC3

PRTC2

PRTC1

PRTC0

VDD_RAM

SEG79

SEG78

SEG77

SEG76

SEG75

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

Pin Name

Pin # I/O

Description

SEG[79..44]

186~216
, 1 ~ 5

O LCD segment SEG[79..44] driver outputs.

SGKY[43..24] 6 ~ 25 O

LCD segments share pads with key scan out SCNO[19..0]. The key scan function of
these pins can be disabled by mask option clearing MO_LCDKEY to `0', then
SGKY[43..24] function as LCD segment driver only. Setting MO_LCDKEY to `1'

King Billion Electronics Co., Ltd

HE84770C

HE80000 SERIES

August 25, 2003

Page 4 of 25

V1.1E

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Pin Name

Pin # I/O

Description

will turn on the key scan function.

PRT14[7..0]/
SEG[23:16]

26 ~ 33

B/
O

8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The
function of the pad can be selected individually by mask options MO_LIO14[7..0].
(`1' for LCD and `0' for I/O).
The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1 for
push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, "1" must be outputted before reading.

PRT15[7..0]/
SEG[15:8]

34 ~ 41

B/
O

8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[15..8]. The
function of the pad can be selected individually by mask options MO_LIO15[7..0].
(`1' for LCD and `0' for I/O).
The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1 for
push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, "1" must be outputted before reading.

PRT17[7..0]/
SEG[7:0]

42 ~ 49

B/
O

8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The
function of the pad can be selected individually by mask options MO_LIO17[7..0].
(`1' for LCD and `0' for I/O).
The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1 for
push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, "1" must be outputted before reading.

COM[31..0] 50 ~ 81 O LCD COMMON Driver pads.
LVL1

P LCD Bias Voltage 1.

LVL2

P LCD Bias Voltage 2

LVL3 84

LCD Bias Voltage 3

LVL4

P LCD Bias Voltage 4

LVL5

P LCD Bias Voltage 5.

LGS2

LCD Drive Voltage Setting

LVP

P Charge Pump Output..

LCAP4A

O Charge Pump Capacitor Pin.

LCAP2B

O Charge Pump Capacitor Pin.

LCAP2A

O Charge Pump Capacitor Pin.

LCAP1A

O Charge Pump Capacitor Pin.

LCAP1B

O Charge Pump Capacitor Pin.

LCAP3A

O Charge Pump Capacitor Pin.

LVREG 95 O

Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns
pumped to LVP. Adjust resistor between LGS1 and LVREG to set LVREG voltage.

LGS1 96

Regulator

Voltage

Setting

LVAG 97

Reference

Voltage

Output.

Fixed 0.9 Volt DC reference voltage

GND

P Power ground Input.

VO 99

DAC Voice Output. Set the bit 1 and clear the bit 0 of VOC (DA = `1' and OP = `0')
register to turn on DAC with VO output.

DAO 100

Alternate output of DAC. Set both bit 1 and bit 0 of VOC register (DA = `1' and OP =
`1') to turn on DAC with DAO output as well as OP comparator.

OPIN 101

Inverting input of OP Amp. Set the bit 0 of VOC register (OP = `1') to turn on OP
comparator.

OPIP

102

Non-inverting input of OP Amp.

OPO

103

O Output of OP Amp.

RSTP_N 104 I

System Reset input pin. Level trigger, active low on this pin will put the chip in reset
state.

FXO,

105, 106 O, External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (`0'

King Billion Electronics Co., Ltd

HE84770C

HE80000 SERIES

August 25, 2003

Page 5 of 25

V1.1E

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Pin Name

Pin # I/O

Description

FXI

B for RC type and `1' for crystal type). For RC type oscillator, one resistor need to be

connected between FXI and GND. For crystal oscillator, one crystal need to be placed
between FXI and FXO. Please refer to application circuit for details.

TSTP_P 107

Test input pin. Please bond this pad and reserve a test point on PCB for debugging.
But for improving ESD, please connect this point with zero Ohm resistor to GND

SXO,
SXI

108, 109

O,
I

External slow clock pins. Slow clock is clock source for LCD display, TIMER1,
Time-Base and other internal blocks. Both crystal and RC oscillator are provided. The
slow clock type can be selected by mask option MO_SXTAL. Choose `0' for RC type
and `1' for crystal oscillator.

VDD 110

Positive power Input. 0.1 �F decoupling capacitors should be placed as close to IC
VDD and GND pads as possible for best decoupling effect.

PRT10[7..0]

111 ~
118

8-bit bi-directional I/O port 10. The output type of I/O pad can be selected by mask
option MO_10PP[7..0] (`1' for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
pad as input pad, "1" must be outputted before reading.

PRTD[7..0]

119 ~
126

8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by
mask option MO_DPP[7..0] (`1' for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, `1' must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt
sources.

GND_PWM 127

O Dedicated Ground for PWM output.

PWM 128

The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as
one to turn on PWM. Using VDD & PWM to drive output device.

PRTC[7..0]

129 ~
136

8-bit bi-directional I/O port C. PRTC[7:4] is shared with Key Scan Dedicated Input
SCNI[3:0]. The Key Scan function can be disabled by clearing MO_LCDKEY mask
option to `0'.
The output type of I/O pad can also be selected by mask option MO_CPP[7..0] (`1'
for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, `1' must be outputted before reading the pin.

VDD_RAM 137

P Dedicated power input for RAM

CMSG[32..79]

138 ~
185

COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads to
be COM drivers or SEG drivers can be selected by mask option MO_COM[0]. Please
refer to LCD driver configuration for details.

I: Input, O: Output, B: Bidirectional, P: Power.

5. LCD RAM Map

There are 4 LCD configurations as determined by mask option MO_COM[1..0]. The functions of
CMSG[79..32] are different in each configuration as listed in the following table.

MO_COM[1..0] Configuration CMSG[79..64] CMSG[63..48] CMSG[47..32]

32 x 128 SEG[80..95] SEG[96..111] SEG[112..127]

48 x 112 SEG[80..95] SEG[96..111] COM[47..32]

64 x 96

SEG[80..95] COM[63..48] COM[47..32]

80 x 80

COM[79..64] COM[63..48] COM[47..32]

King Billion Electronics Co., Ltd

HE84770C

HE80000 SERIES

August 25, 2003

Page 6 of 25

V1.1E

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CMSG32

COM32

SEG127

CMSG33

COM33

SEG126

CMSG34

COM34

SEG125

CMSG35

COM35

SEG124

CMSG36

COM36

SEG123

CMSG37

COM37

SEG122

CMSG38

COM38

SEG121

CMSG39

COM39

SEG120

CMSG40

COM40

SEG119

CMSG41

COM41

SEG118

CMSG42

COM42

SEG117

CMSG43

COM43

SEG116

CMSG44

COM44

SEG115

CMSG45

COM45

SEG114

CMSG46

COM46

SEG113

CMSG47

COM47

SEG112

CMSG48

COM48

SEG111

CMSG49

COM49

SEG110

CMSG50

COM50

SEG109

CMSG51

COM51

SEG108

CMSG52

COM52

SEG107

CMSG53

COM53

SEG106

CMSG54

COM54

SEG105

CMSG55

COM55

SEG104

CMSG56

COM56

SEG103

CMSG57

COM57

SEG102

CMSG58

COM58

SEG101

CMSG59

COM59

SEG100

CMSG60

COM60

SEG99

CMSG61

COM61

SEG98

CMSG62

COM62

SEG97

CMSG63

COM63

SEG96

CMSG64

COM64

SEG95

CMSG65

COM65

SEG94

CMSG66

COM66

SEG93

CMSG67

COM67

SEG92

CMSG68

COM68

SEG91

CMSG69

COM69

SEG90

CMSG70

COM70

SEG89

CMSG71

COM71

SEG88

CMSG72

COM72

SEG87

CMSG73

COM73

SEG86

CMSG74

COM74

SEG85

CMSG75

COM75

SEG84

CMSG76

COM76

SEG83

CMSG77

COM77

SEG82

CMSG78

COM78

SEG81

CMSG79

COM79

SEG80

64X96

80X80

COMXSEG

32X128

48X112

The RAM Maps of all four different LCD configurations are as the following:

32 COM:

Page

SEG

[7:0]

SEG

[15:8]

SEG

[23:16]

SEG

[31:24]

SEG

[39:32]

SEG

[47:40]

SEG

[55:48]

SEG

[63:56]

COM0 7E0H 7C0H 7A0H 780H 760H 740H 720H 700H
COM1 7E1H 7C1H 7A1H 781H 761H 741H 721H 701H

: : : : : : : : :

COM15

7EFH 7CFH 7AFH 78FH 76FH 74FH 72FH 70FH

COM16 7F0H 7D0H 7B0H 790H 770H 750H 730H 710H

: : : : : : : : :

COM30 7FEH 7DEH 7BEH 79EH 77EH 75EH 73EH 71EH
COM31 7FFH 7DFH 7BFH 79FH 77FH 75FH 73FH 71FH

Page

SEG

[71:64]

SEG

[79:72]

SEG

[87:80]

SEG

[95:88]

SEG

[103:96]

SEG

[111:104]

SEG

[119:112]

SEG

[127:120]

COM0 6E0H 6C0H 6A0H 680H 660H 640H 620H 600H
COM1 6E1H 6C1H 6A1H 681H 661H 641H 621H 601H

: : : : : : : : :

COM15

6EFH 6CFH 6AFH 68FH 66FH 64FH 62FH 60FH

COM16 6F0H 6D0H 6B0H 690H 670H 650H 630H 610H

King Billion Electronics Co., Ltd

HE84770C

HE80000 SERIES

August 25, 2003

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V1.1E

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: : : : : : : : :

COM30 6FEH 6DEH 6BEH 69EH 67EH 65EH 63EH 61EH
COM31 6FFH 6DFH 6BFH 69FH 67FH 65FH 63FH 61FH

48 COM

Page 7,6

SEG[7:0] SEG[15:8] SEG[23:16] SEG[31:24] SEG[39:32] SEG[47:40] SEG[55:48]

COM0 7C0H 780H 740H 700H 6C0H 680H 640H
COM1 7C1H 781H 741H 701H 6C1H 681H 641h

: : : : : : : :

COM15

7CFH 78FH 74FH 70FH 6CFH 68FH 64FH

COM16

7D0H 790H 750H 710H 6D0H 690H 650H

: : : : : : : :

COM31

7DFH 79FH 75FH 71FH 6DFH 69FH 65FH

COM32 7E0H 7A0H 760H 720H 6E0H 6A0H 660H

: : : : : : : :

COM46 7EEH 7AEH 76EH 72EH 6EEH 6AEH 66EH
COM47 7EFH 7AFH 76FH 72FH 6EFH 6AFH 66FH

Page

6, 5, 4

SEG

[63:56]

SEG

[71:64]

SEG

[79:72]

SEG

[87:80]

SEG

[95:88]

SEG

[103:96]

SEG

[111:104]

COM0 600H 5C0H 580H 540H 500H 4C0H 480H
COM1 601H 5C1H 581H 541h 501H 4C1H 481H

: : : : : : : :

COM15 60FH 5CFH 58FH 54FH 50FH 4CFH 48FH
COM16 610H 5D0H 590H 550H 510H 4D0H 490H

: : : : : : : :

COM31 61FH 5DFH 59FH 55FH 51FH 4DFH 49FH
COM32 620H 5E0H 5A0H 560H 520H 4E0H 4A0H

: : : : : : : :

COM46 62EH 5EEH 5AEH 56EH 52EH 4EEH 4AEH
COM47 62FH 5EFH 5AFH 56FH 52FH 4EFH 4AFH

64 COM

Page 7,6

SEG[7:0]

SEG[15:8]

SEG[23:16]

SEG[31:24]

SEG[39:32] SEG[47:40]

COM0 7C0H 780H 740H 700H 6C0H 680H
COM1 7C1H 781H 741H 701H 6C1H 681H

: : : : : : :

COM15

7CFH 78FH 74FH 70FH 6CFH 68FH

COM16

7D0H 790H 750H 710H 6D0H 690H

: : : : : : :

COM31

7DFH 79FH 75FH 71FH 6DFH 69FH

COM32 7E0H 7A0H 760H 720H 6E0H 6A0H

: : : : : : :

COM47 7EFH 7AFH 76FH 72FH 6EFH 6AFH
COM48 7F0H 7B0H 770H 730H 6F0H 6B0H

: : : : : : :

COM62 7FEH 7BEH 77EH 73EH 6FEH 6BEH
COM63 7FFH 7BFH 77FH 73FH 6FFH 6BFH

King Billion Electronics Co., Ltd

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HE80000 SERIES

August 25, 2003

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V1.1E

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Page 6, 5

SEG[55:48]

SEG[63:56]

SEG[71:64]

SEG[79:72]

SEG[87:80] SEG[95:88]

COM0 640H 600H 5C0H 580H 540H 500H
COM1 641H 601H 5C1H 581H 541H 501H

: : : : : : :

COM15 64FH 60FH 5CFH 58FH 54FH 50FH
COM16 650H 610H 5D0H 590H 550H 510H

: : : : : : :

COM31 65FH 61FH 5DFH 59FH 55FH 51FH
COM32 660H 620H 5E0H 5A0H 560H 520H

: : : : : : :

COM47 66FH 62FH 5EFH 5AFH 56FH 52FH
COM48 670H 630H 5F0H 5B0H 570H 530H

: : : : : : :

COM62 67EH 63EH 5FEH 5BEH 57EH 53EH
COM63 67FH 63FH 5FFH 5BFH 57FH 53FH

80 COM

Page

7:3

SEG

[7:0]

SEG

[15:8]

SEG

[23:16]

SEG

[31:24]

SEG

[39:32]

SEG

[47:40]

SEG

[55:48]

SEG

[63:56]

SEG

[71:64]

SEG

[79:72]

COM0 780H 700H 680H 600H 580H 500H 480H 400H 380H 300H
COM1 781H 701H 681H 601H 581H 501H 481H 401H 381H 301H

: : : : : : : : : : :

COM15 78FH 70FH 68FH 60FH 58FH 50FH 48FH 40FH 38FH 30FH
COM16 790H 710H 690H 610H 590H 510H 490H 410H 390H 310H

: : : : : : : : : : :

COM31 79FH 71FH 69FH 61FH 59FH 51FH 49FH 41FH 39FH 31FH
COM32 7A0H 720H 6A0H 620H 5A0H

520H 4A0H

420H 3A0H

320H

: : : : : : : : : : :

COM47 7AFH 72FH 6AFH 62FH 5AFH

52FH 4AFH

42FH 3AFH

32FH

COM48 7B0H 730H 6B0H 630H 5B0H

530H 4B0H

430H 3B0H

330H

: : : : : : : : : : :

COM62 7BFH 73FH 6BFH 63FH 5BFH

53FH 4BFH

43FH 3BFH

33FH

COM63 7C0H 740H 6C0H 640H 5C0H

540H 4C0H

440H 3C0H

340H

: : : : : : : : : : :

COM78 7CEH 74EH 6CEH 64EH 5CEH

54EH 4CEH

44EH 3CEH

34EH

COM79 7CFH 74FH 6CFH 64FH 5CFH

54FH 4CFH

44FH 3CFH

34FH

6. LCD Power Supply

The built-in LCD power supply is equipped with input voltage regulator, voltage multiplier and bias
voltage generating circuit with active buffer instead of passive resistor voltage dividing network. The
input voltage is regulated to LVREG using the internally generated LVAG as reference voltage. LVREG
can be adjusted by resistor between LGS1 and LVREG.

LVREG adjustment guideline: First, the level of VDD must be 0.3 volt higher than LVREG even at the
end of battery life for the regulator to function properly. For example, if the VDD is expected to drop to
2.2 volts when battery is low, then the level of LVREG can only be set at 1.9 volts max. Secondly, the
higher the level of LVREG, the less multiples it requires to pump LVP to same level. For example, to

King Billion Electronics Co., Ltd

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HE80000 SERIES

August 25, 2003

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V1.1E

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pump the 2.25 volts to 9 volts requires 4 times multiplier; to pump the 3 volts to 9 volts requires only 3
time multiplier which consumes less power. So it is advisable not to adjust the LVREG to an unnecessary
low level.
Voltage multiplication: The LVREG is then multiplied by 3, 4, or 5 times, depending on external
capacitors configurations as shown below, to generate LVP. Please note that LVP must be lower than 9
volts to prevent chip from breaking down.

LVL1

LVL2

LVL3

LVL4

LVL5

LGS2

LVP

LCAP4A

LCAP2B

LCAP2A

LCAP1A

LCAP1B

LCAP3A

LVREG

LGS1

LVAG

0.1uF

4.7uF

0.1uF

4.7uF

0.1uF

4.7uF

10uF

4.7uF

0.1uF

4.7uF

10uF

x4 multiplier

x5 multiplier

x3 multiplier

The LVP is then regulated to generated LVL1 ~ LVL5. LVL5 can be adjusted by the resistor between
LGS2 and LV5. Be sure to leave at least 0.3 volt between LVP and LV5 for the regulator circuit to
function properly. The formula is:

LVL5 = (1 + R2/80K) x 0.9V

Different duties require different bias settings. There is some theoretical correspondence between the
Duty and Bias Setting. However, it is better to use it as starting point and adjust it with real LCD panel
connected to it to determine the final setting. The theoretic relationship between the duty and bias setting
as following:

Duty Cycle Normal Bias Alternative Bias

32 duty

1/7

1/7.5

48 duty

1/8

1/7.5, 1/8.5

64 duty

1/9

1/8.5, 1/9.5

80 duty

1/10

1/9.5, 1/10.5

The bias setting is made by mask option MO_LBSR[2..0].

MO_LBSR[2..0] Bias Setting

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Page 10 of 25

V1.1E

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000

1/7

001 1/7.5
010 1/8
011 1/8.5
100 1/9
101 1/9.5
110 1/10
111 1/10.5

6.1. LCDC Control register

The gray scale of the LCD driver can be adjusted by GRAY field of LCD. The LCD panel can be blanked
by setting the BLANK field of LCDC register. LCD driver can be totally turned off by clearing LCDE bit
of LCDC.

LCDC

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Field

- - -

GRAY

BLANK

LCDE

Reset

- - - - - - 1 0

Field Value

Function

GRAY

000 LCD is darkest.

111 LCD is lightest.

BLANK 0 normal

display

LCD display blanked. The COM signals of LCD driver output inactive levels
(LVL4 and LVL1) while SEG signals output normal display patterns.

LCDE

LCD driver disabled, LCD driver has no output signal.

LCD driver Enabled

Please note that LCD driver must be turned off before the MCU goes into sleep mode. In other words,
user must clear the bit 0 (LCDE bit) of LCDC to turn off LCD driving circuit before setting bit6 of OP1
to enter sleep mode. Large current might happen if the procedure is not followed.

Please note that LCD driver uses slow clock as clock source. The LCD display would not display
normally if it worked in Fast clock only mode as the LCD refresh action would be too fast.

7. Oscillators

The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to
choose from. So that system designer can select oscillator types based on the cost target, timing accuracy
requirements etc. Crystal, Resonator or the RC oscillator can be used as fast clock source, components
should be placed as close to the pins as possible. The type of oscillator used is selected by mask option
MO_FXTAL.

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V1.1E

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PRT170

SEG0

PRT170

PRT171

SEG1

PRT171

PRT172

SEG2

PRT172

PRT173

SEG3

PRT173

PRT174

SEG4

PRT174

PRT175

SEG5

PRT175

PRT176

SEG6

PRT176

PRT177

SEG7

PRT177

PRT150

SEG8

PRT150

PRT151

SEG9

PRT151

PRT152

SEG10

PRT152

PRT153

SEG11

PRT153

PRT154

SEG12

PRT154

PRT155

SEG13

PRT155

PRT156

SEG14

PRT156

PRT157

SEG15

PRT157

PRT140

SEG16

PRT140

PRT141

SEG17

PRT141

PRT142

SEG18

PRT142

PRT143

SEG19

PRT143

PRT144

SEG20

PRT144

PRT145

SEG21

PRT145

PRT146

SEG22

PRT146

PRT147

SEG23

PRT147

LIO17=1

LIO17=0

LIO15=0

LIO15=1

LIO14=0

LIO14=1

Following table is the setting for MO_LIO?[...] and MO_?PP[...] and others related to LCD display

setting and pin assignment features.

MO_LIO?[...] MO_?PP[...]

I/O Port

LCD Pin

0 0

Open-drain

output

0 1

Push-pull

output

1 0 -- xx

1 1 --

LCD

Display

--: Function not available.
xx: Displayable, but may have abnormal leakage current, do not use.

9. Key Scan Circuit

The built-in 4x20 hardware keyboard scan circuit helps to reduce the pin counts where application
requires large key matrix and high LCD pixel count as well as the firmware effort. As key-scan pins are
shared with LCD segment and PRTC4 ~ PRTC7 pins, it is advisable to put resistors between segment pins
and key matrix to avoid shorting the segment pins when two or more keys in the same row are pressed
simultaneously. Two key can be detected simultaneously and the first detected key code is stored in
KEY0 register and the second in KEY1 register respectively. The key code for each key location is listed
in the following table.

Key Loc SCNI0 SCNI1 SCNI2 SCNI3
SCNO0 0x80

0xA0 0xC0 0xE0

SCNO1 0x81

0xA1 0xC1 0xE1

SCNO2 0x82

0xA2 0xC2 0xE2

SCNO3 0x83

0xA3 0xC3 0xE3

SCNO4 0x84

0xA4 0xC4 0xE4

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V1.1E

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program can operate normally. When abnormal conditions happen to cause the MCU to divert from

normal path, the WDT counter will not be cleared and reset signal will be generated.

WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is

same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated

in Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1

clock has stopped.)

14. Digital-to-Analog Converter

The Digital-to-Analog converter (DAC) converts the 7-bit unsigned speech data written to PWMC to
proportional current output.

PWMC register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DA & PWM Data

DA and PWM output value

Control

PWM O/P driver

PWME

There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by
VOC register when it is enabled. The VO output is primarily intended for speech generation, although it
is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to
function as an Analog-to-Digital Converter as required in applications such as speech recording, speech
recognition or sensor interfaces.

OPO

OPIP

OPIN

DAO

PWMC[DATA]

VOC[DAC]

VOC[OP]

DAC

The DAC is enabled by DAC bit of VOC register. Please note that the DAC bit of VOC register will be
automatically cleared when the system enter Idle or Sleep mode. So it needs to be set again when
returning to Normal mode.

VOC register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Field

- - - - -

PWM

DAC

Reset

- - - - - 0 0 0

Bit Name Value Function

description

1 DA

Enable

1 DAC

0 DA

Disable

King Billion Electronics Co., Ltd

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V1.1E

This specification is subject to change without notice. Please contact sales person for the latest version before use.

15. Pulse-Width Modulation

The pulse-width modulator (PWM) converts 7-bit unsigned speech data written to PWMC data register to
proportional duty cycle of PWM output. PWM module shares the PWMC data register with
Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is
enabled, it generates signal with duty ratio in proportion to the DA value.

DA = 0x20

DA = 0x80

DA = 0xE0

1 subframe

The PWM bit of VOC register controls register to enable the circuit and output driver. When PWM bit of
VOC is `0', PWME bit and output drivers settings are both cleared. To use PWM for voice output, PWM
bit has to be set to `1' first, then set PWME bit and enable output driver by setting the driver number. If
PWM bit is disabled and enabled again, the setting for driver and PWME bit will be clear.

The Fast Clock is gated through PWME bit of PWMC command register to provide the clock source of
PWM circuit when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct
PWM signal in Slow clock only mode.

When the program enters into Sleep mode or Idle mode, it will automatically turn off all voice outputs by
clearing VOC[2..1] to "00". To activate voice output again when returning to Normal Mode, the VOC
register needs to be set again.

The PWM output volume can be adjusted by command register PWMC[6..4]. The bit 6 and 5 control 2
time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the
internal drivers, the sound level of PWM output can be turned up and down. Please note that this
adjustment apply only to PWM, but not DA output.

PWM output driver selection

PWMC[6..4] Number of Driver

000 off

001 1

010 2

011 3

100 2

101 3

110 4

111 5

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HE84770C

HE80000 SERIES

August 25, 2003

Page 21 of 25

V1.1E

This specification is subject to change without notice. Please contact sales person for the latest version before use.

16. Absolute Maximum Rating

Item Sym.

Rating

Condition

Supply Voltage

-0.5V ~ 4.0V

LCD operating Voltage

LVP

< 8 Volts

Input Voltage

-0.5V ~ V

+0.5V

Output Voltage

-0.5V

+0.5V

Operating Temperature

�

C ~ 70

�

Storage Temperature

-50

�

C ~ 100

�

17. Recommended Operating Conditions

Item Sym.

Rating

Condition

Supply Voltage

2.4V ~ 3.6V

0.9 V

~ V

Input Voltage

0.0V ~ 0.1 V

8MHz V

=3.0V

Operating Frequency

MAX

6MHz V

=2.4V

Operating Temperature

�

C ~ 70

�

Storage Temperature

-50

�

C ~ 100

�

18. AC/DC Characteristics

Testing Condition : TEMP=25, VDD=3V�10%

Parameters Symbol

Min.

Typ.

Max.

Unit

Condition

Power consumption
Normal mode current

FAST

1.5

2M external R/C fast clock

Slow mode Current

SLOW

15 25

�A

32768 Hz slow clock with LCD
disabled

Idle mode Current

IDLE

�A

32768 Hz slow clock with LCD
disabled

Sleep mode Current

SLEEP

1 �A

200

220

LVP=3*LVREG

250

275

LVP=4*LVREG

Additional Current if LCD
ON

LCD

300

330

�A

LVP=5*LVREG

I/O specification
Input High Voltage

0.8

VDD Input

Pins

Input Low Voltage

0.2

VDD Input

Pins

Input Hysteresis Width

HYS

1/3

VDD

I/O, RSTP_N Threshold = 2/3xVDD
(Input from low to high), Threshold =
1/3xVDD (Input from high to low)

Output Source Current

�A

Output drive high

*1,

=2.0V

Output Sink Current

OL1

1.0

Output drive low, V

=0.4V

Input Low Current

IL1

20 �A

RSTP_N, V

= GND, Pull high

Internally

Input Low Current

IL2

100 �A

I/O, V

=GND, if pull high Internally by

user

PWM and DAC
PWM Output Current

PWM

10 14 mA

PWM

With 32 Loading

King Billion Electronics Co., Ltd

HE84770C

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August 25, 2003

Page 23 of 25

V1.1E

This specification is subject to change without notice. Please contact sales person for the latest version before use.

19. Application Circuit

VDD

CMSG32

COM32

SEG127

CMSG33

COM33

SEG126

PRT170

SEG0

PRT170

CMSG34

COM34

SEG125

PRT171

SEG1

PRT171

CMSG35

COM35

SEG124

PRT172

SEG2

PRT172

CMSG36

COM36

SEG123

PRT173

SEG3

PRT173

CMSG37

COM37

SEG122

PRT174

SEG4

PRT174

CMSG38

COM38

SEG121

PRT175

SEG5

PRT175

CMSG39

COM39

SEG120

PRT176

SEG6

PRT176

CMSG40

COM40

SEG119

PRT177

SEG7

PRT177

CMSG41

COM41

SEG118

CMSG42

COM42

SEG117

CMSG43

COM43

SEG116

SEG48

CMSG44

COM44

SEG115

SEG47

PRT150

SEG8

PRT150

CMSG45

COM45

SEG114

SEG46

PRTC0

PRT151

SEG9

PRT151

CMSG46

COM46

SEG113

SEG45

PRTC1

PRT152

SEG10

PRT152

CMSG47

COM47

SEG112

SEG44

PRTC2

PRT153

SEG11

PRT153

CMSG48

COM48

SEG111

SEG43

PRTC3

PRT154

SEG12

PRT154

CMSG49

COM49

SEG110

SEG42

PRTC4

PRT155

SEG13

PRT155

CMSG50

COM50

SEG109

SEG41

PRTC5

PRT156

SEG14

PRT156

CMSG51

COM51

SEG108

SEG40

PRTC6

PRT157

SEG15

PRT157

CMSG52

COM52

SEG107

SEG39

PRTC7

CMSG53

COM53

SEG106

SEG38

PWM

CMSG54

COM54

SEG105

SEG37

CMSG55

COM55

SEG104

SEG36

PRTD0

PRT140

SEG16

PRT140

CMSG56

COM56

SEG103

SEG35

PRTD1

PRT141

SEG17

PRT141

CMSG57

COM57

SEG102

SEG34

PRTD2

PRT142

SEG18

PRT142

CMSG58

COM58

SEG101

SEG33

PRTD3

PRT143

SEG19

PRT143

CMSG59

COM59

SEG100

SEG32

PRTD4

PRT144

SEG20

PRT144

CMSG60

COM60

SEG99

SEG31

PRTD5

PRT145

SEG21

PRT145

CMSG61

COM61

SEG98

SEG30

PRTD6

PRT146

SEG22

PRT146

CMSG62

COM62

SEG97

SEG29

PRTD7

PRT147

SEG23

PRT147

CMSG63

COM63

SEG96

SEG28

PRT100

CMSG64

COM64

SEG95

SEG27

PRT101

CMSG65

COM65

SEG94

SEG26

PRT102

CMSG66

COM66

SEG93

SEG25

PRT103

CMSG67

COM67

SEG92

SEG24

PRT104

CMSG68

COM68

SEG91

PRT147

PRT105

CMSG69

COM69

SEG90

PRT146

PRT106

CMSG70

COM70

SEG89

PRT145

PRT107

CMSG71

COM71

SEG88

PRT144

CMSG72

COM72

SEG87

SXI

CMSG73

COM73

SEG86

CMSG74

COM74

SEG85

CMSG75

COM75

SEG84

SXI

CMSG76

COM76

SEG83

CMSG77

COM77

SEG82

CMSG78

COM78

SEG81

CMSG79

COM79

SEG80

SXO

FXI

FXO

SXI

SGKY24

SCNO0

SGKY25

SCNO1

SGKY26

SCNO2

SGKY27

SCNO3

SGKY41

SCNO17

SGKY42

SCNO18

SXO

SGKY43

SCNO19

PRTC4

SCNI0

PRTC5

SCNI1

LVL1

PRTC6

SCNI2

LVL2

PRTC7

SCNI3

LVL3

LVL4

LVL5

LGS2

LVP

LCAP4A

LCAP2B

LCAP2A

LCAP1A

LCAP1B

LCAP3A

LVREG

LGS1

LVAG

SEG

PR
T1
4

SEG

PR
T1
4

SEG

PR
T1
4

SEG

PR
T1
4

SEG

PR
T1
5

SEG

PR
T1
5

SEG

PR
T1
5

SEG

PR
T1
5

SEG

PR
T1
5

SEG

PR
T1
5

SEG

PR
T1
5

SEG

PR
T1
5

SEG

PR
T1
7

SEG

PR
T1
7

SEG

PR
T1
7

SEG

PR
T1
7

SEG

PR
T1
7

SEG

PR
T1
7

SEG

PR
T1
7

SEG

PR
T1
7

SEG

COM

SEG

COM

SEG

COM

SEG

COM

SEG

COM

SEG

COM

SEG

COM

SEG

COM

SEG

COM

SEG

COM

SEG

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

COM

CM
S

LV
L1

CM
S

LV
L2

CM
S

LV
L3

CM
S

LV
L4

CM
S

LV
L5

CM
S

LGS

CM
S

LV
P

CM
S

AP4

CM
S

AP2

CM
S

AP2

CM
S

AP1

CM
S

AP1

CM
S

AP3

CM
S

LV
RE
G

CM
S

LGS

CM
S

VAG

CM
S

DA
O

CM
S

OP
I
N

CM
S

OP
I
P

CM
S

OP
O

CM
S

RS
T

CM
S

FXO

CM
S

FXI

CM
S

SXO

HE84770

2
3

5
6

8
9

11
12

14
15

18
19

21
22

24
25

27
28

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

SEG48

SEG47

SEG46
SEG45

SEG44

SGKY43
SGKY42

SGKY41

SGKY40
SGKY39

SGKY38

SGKY37

SGKY36
SGKY35

SGKY34

SGKY33
SGKY32

SGKY31

SGKY30
SGKY29

SGKY28

SGKY27
SGKY26

SGKY25

SGKY24
PRT147

PRT146

PRT145
PRT144

COM

C0M

COM

LGS

AP4

AP2

AP1

AP3

LGS

VAG

GND

I
N

I
P

FXO

FXI

TSTP_P

SXO

SXI

VDD

PRT107

PRT106

PRT105

PRT104

PRT103

PRT102

PRT101

PRT100

PRTD7

PRTD6

PRTD5

PRTD4

PRTD3

PRTD2

PRTD1

PRTD0

GND_PWM

PWM

PRTC7

PRTC6

PRTC5

PRTC4

PRTC3

PRTC2

PRTC1

PRTC0

VDD_RAM

SEG

20P

32768Hz

47K

0.1uF

47uF

260K

560K

4.7uF

3.0V

0.1uF

4.7uF

0.1uF

4MHz

15P

0.1uF

10uF

4.7uF

0.1uF

4.7uF

10uF

4.7uF

0.1uF

4.7uF

0.1uF

1uF

10uF

4.7uF

0.1uF

4.7uF

BUZZER

0.1uF

RC Osc.

x4 multiplier

x5 multiplier

x3 multiplier

64X96

80X80

COMXSEG

32X128

48X112

....

LIO17=1

LIO17=0

LIO15=0

LIO15=1

LIO14=0

LIO14=1

King Billion Electronics Co., Ltd

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HE80000 SERIES

August 25, 2003

Page 24 of 25

V1.1E

This specification is subject to change without notice. Please contact sales person for the latest version before use.

20. Important Note

1. To access any data ROM (DROM) of which address is larger than 64KB, users must update TPP first,

TPH 2nd and TPL lastly. Only follow this order, the pre-charge circuit of DROM will work correctly.
Since the Data ROM is a low speed ROM. 5us waiting time is necessary before LDV instruction is
executed to access the DROM. Note this 5us delay can't be emulated in the developing tools (ICE and
KBIDS) and the 5us delay should be added by firmware.

2. LCD driving circuit must be turn off before IC enters into sleep mode.

3. Please bonds the TSTP_P, RSTP_N and PRTD[7:0] with test point on PCB (can be soldered and

probed) as you can. If necessary, some IC testing can be done on the PCB. The following figure is an
example (Testing point with through hole).

4. LVP must small than 8.5 Volt. Otherwise IC may breakdown.

5. The LCD voltage adjustment mechanism shall be reserved for LV5 voltage fine-tunes; since it's possible

there is some variation in LV5 voltage due to IC manufacture process variation. User can use
variable-resistor to adjust the LV5 voltage or use some tools to detect the LV5 and then select a proper
resistor. Please refer to application note AN025 for the detailed description.

6. Users must call the library "swap_page" in the file swappage.asm of AN029. The real IC register is

different from ICE4.x or ICE5.x. This subroutine makes sure that users can run on both real IC and
ICE for page swapping.

.area swapping_variable(data)

_mapreg1:: .ds 1 ;store page register(R1Bh)

_mapreg2:: .ds 1 ;store page register(R1Ch)

.area

swapping_page(code,pag0)

;======================================================

;swap page function

;======================================================

Электронный компонент: HE84770C