Rev 2.3 - 1/15/96
8-65
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PRELIMINARY
Features
n
High-density 2 megabyte Static RAM module
n
Low profile 72-pin ZIP (Zig-zag In-line vertical
Package) or 72-pin SIMM (Single In-line Memory
Module)
n
Fast access time: 15 ns (max.)
n
Surface mounted plastic components on an epoxy
laminate (FR-4) substrate Single 5V (
10%) power
supply
n
Multiple V
SS
pins and decoupling capacitors for
maximum noise immunity
n
Inputs/outputs directly TTL compatible
Description
The PDM4M4110 is a 512K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate
using four (4) 512K x 8 static RAMs in plastic SOJ
packages. Availability of four chip select lines pro-
vides byte access. The PDM4M4110 is available with
access times as fast as 15 ns with minimal power
consumption.
The PDM4M4110 is packaged in a 72-pin FR-4 ZIP
(Zig-zag In-line vertical Package) or a 72-pin SIMM
(Single In-line Memory Module). The ZIP configura-
tion allows 72 pins to be placed on a package 3.95"
long and 0.250" wide. At only 0.600" high, this low-
profile package is ideal for systems with minimum
board spacing. The SIMM configuration allows use of
edge mounted sockets to secure the module.
All inputs and outputs of the PDM4M4110 are TTL
compatible and operate from a single 5V supply. Mul-
tiple ground pins and on board decoupling capacitors
provide maximum immunity from noise.
Four identification pins (PD0, PD1, PD2, PD3) are pro-
vided for applications in which different density
versions of the module are used. In this way, the tar-
get system can read the respective levels of PD0, PD1,
PD2, PD3 to determine a 512K depth.
PDM4M4110
512K x 32 CMOS
Static RAM Module
Functional Block Diagram
I/O31-I/O0
8
8
8
8
CS
1
CS
2
CS
3
CS
4
19
4
A18-A0
WE
OE
PD3-PD0
512K x 32
RAM
PDM4M4110
8-66
Rev 2.3 - 1/15/96
PRELIMINARY
Pin Configuration
(1)
NOTE:
1. Pins 3, 4, 6, and 7 (PD0, PD1, PD02, and PD3
respectively) are read by the user to determine the
density of the module. If PD0 reads NC, PD1 reads
NC, PD2 reads OPEN, PD3 reads NC then the
module has a 512K depth.
Pin Assignment
Pin
Signal
I/O31-I/O0
Data Inputs/Outputs
A18-A0
Addresses
CS
4-
CS
1
Chip Selects
WE
Write Enable
OE
Output Enable
PD3-PD0
Depth Identification
V
CC
Power
V
SS
Ground
NC
No Connect
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD3
PD0
I/O0
I/O1
I/O2
I/O3
Vcc
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS
1
CS
3
A16
Vss
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
Vss
NC
NC
NC
PD2
Vss
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
Vss
A15
CS
2
CS
4
A17
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
Vcc
A6
I/O28
I/O29
I/O30
I/O31
A18
NC
ZIP, SIMM
TOP VIEW
PD0 - NC
PD1 - NC
PD2 - OPEN
PD3 - NC
PDM4M4110
Rev 2.3 - 1/15/96
8-67
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PRELIMINARY
Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
V
SS
Supply Voltage
0
0
0
V
Commercial
Ambient Temperature
0
25
70
C
Absolute Maximum Ratings
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Rating
Com'l.
Ind.
Unit
V
TERM
Terminal Voltage with Respect to V
SS
0.5 to +7.0
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
10 to +85
10 to +85
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
T
A
Operating Temperature
0 to +70
0 to +70
C
P
T
Power Dissipation
1.0
1.0
W
I
OUT
DC Output Current
50
50
mA
Truth Table
Mode
CS
OE
WE
Output
Power
Deselect/
Power-down
H
X
X
High-Z
Standby
Read
L
L
H
DATA
OUT
Active
Write
L
X
L
DATA
IN
Active
Deselect
L
H
H
High-Z
Active
PDM4M4110
8-68
Rev 2.3 - 1/15/96
PRELIMINARY
DC Electrical Characteristics
(V
CC
= 5.0V
10%, T
A
= 0
C to +70
C)
NOTE
1. V
IL
= 2.0V for pulse widths less than 10 ns, once per cycle.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
LI
Input Leakage Current
(Address and Control)
V
CC
= Max.,V
IN
= V
SS
to V
CC
--
40
A
I
LI
Input Leakage Current
(Data)
V
CC
= Max., V
IN
= V
SS
to V
CC
--
10
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
, V
CC
= Max.,
CS
= V
IH
--
10
A
V
OL
Output Low Voltage
I
OL
= 8 mA, V
CC
= Min.
--
0.4
V
V
OH
Output High Voltage
I
OL
= 4 mA, V
CC
= Min.
2.4
--
V
V
IH
Input High Voltage
2.2
6.0
V
V
IL
Input Low Voltage
0.5
(1)
0.8
V
Power Supply Characteristics
NOTE
1. Preliminary specification only.
Symbol
Parameter
Max
(1)
Unit
I
CC
Operating Current
CS
= V
IL
, V
CC
= Max., f = f
MAX
, Outputs Open
680
mA
I
SB
Standby Current
CS
V
IH
, V
CC
= Max., f = f
MAX
, Outputs Open
160
mA
I
SB1
Full Standby Current
CS
V
CC
0.2V,
f = 0, V
IN
> V
CC
0.2V or < 0.2V
60
mA
Capacitance
(1)
(T
A
= +25
C, f = 1.0 MHz)
NOTE
1. This parameter is determined by device characteristics but is not production tested.
Symbol Parameter
Max.
Unit
C
IN(D)
Input Capacitance, (Data) V
IN
= 0V
12
pF
C
IN(A)
Input Capacitance, (Address and Control) V
IN
= 0V
40
pF
C
OUT
Input Capacitance, V
OUT
= 0V
12
pF
PDM4M4110
Rev 2.3 - 1/15/96
8-69
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PRELIMINARY
AC Test Conditions
Input Pulse Levels
V
SS
to 3.0V
Input Rise/Fall Times
5 ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 and 2
255
480
30 pF*
+5V
DATA
OUT
* Including scope and jig capacitances
Figure 1. Output Load
255
480
5 pF*
+5V
DATA
OUT
* Including scope and jig capacitances
Figure 2. Output Load
(for t
OHZ
, t
CHZ
, t
OLZ
, and t
CLZ
)
PDM4M4110
8-70
Rev 2.3 - 1/15/96
PRELIMINARY
AC Electrical Characteristics
(Vcc = 5V
10%, T
A
= 0
C to +70
C)
NOTE
1. This parameter is determined by device characteristics but is not production tested.
2. t
AS
= 0 ns for
CS
controlled write cycles. t
DH
, t
WR
= 3 ns for
CS
controlled write cycles
Symbol
Parameter
PDM4M4110SXXZ, PDM4M4110SXXM
Unit
-15 ns
-20 ns
-25 ns
-35 ns
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
15
--
20
--
25
--
35
--
ns
t
AA
Address Access Time
--
15
--
20
--
25
--
35
ns
t
ACS
Chip Select Access Time
--
15
--
20
--
25
--
35
ns
t
CLZ
(1)
Chip Select to Output inLow-Z
5
--
3
--
3
--
3
--
ns
t
OE
Output Enable to Output Valid
--
6
--
10
--
12
--
15
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
--
0
--
0
--
0
--
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
--
10
--
12
--
14
--
16
ns
t
OHZ
(1)
Output Disable to Output in High-Z
--
6
--
8
--
10
--
12
ns
t
OH
Output Hold from Address Change
3
--
3
--
3
--
3
--
ns
t
PU
(1)
Chip Select to Power-Up Time
0
--
0
--
0
--
0
--
ns
t
PD
(1)
Chip Deselect to Power-Down Time
--
15
--
20
--
25
--
35
ns
Write Cycle
t
WC
Write Cycle Time
15
--
20
--
25
--
35
--
ns
t
CW
Chip Select to End of Write
13
--
18
--
20
--
25
--
ns
t
AW
Address Valid to End of Write
13
--
18
--
20
--
25
--
ns
t
AS
(2)
Address Setup Time
3
--
3
3
--
3
--
ns
t
WP
Write Pulse Width
13
--
15
--
17
--
22
--
ns
t
WR
(2)
Write Recovery Time
0
--
0
--
0
--
0
--
ns
t
WHZ
(1)
Write Enable to Output in High-Z
--
8
--
8
--
13
--
15
ns
t
DW
Data to Write Time Overlap
10
--
12
--
15
--
20
--
ns
t
DH
(2)
Data Hold from Write Time
0
--
0
--
0
--
0
--
ns
t
OW
(1)
Output Active from End of Write
2
--
2
--
2
--
2
--
ns
PDM4M4110
Rev 2.3 - 1/15/96
8-71
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PRELIMINARY
Timing Waveforms of Read Cycle No.1
(1)
Timing Waveforms of Read Cycle No.2
(1,2,4)
Timing Waveforms of Read Cycle No.3
(1,3,4)
NOTES 1
WE
is HIGH for Read Cycle.
2. Device is continuously selected.
CS
= V
IL
.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
= V
IL
.
5. Transition is measured
200 mV for steady state. This parameter is
determined by device characteristics but is not production tested.
t
AA
t
RC
ADDRESS
t
OE
D
OUT
t
OH
t
CHZ(5)
t
OHZ(5)
t
ACS
t
CLZ(5)
CS
OE
t
OLZ(5)
t
AA
t
RC
ADDRESS
D
OUT
t
OH
t
OH
Previous Data Valid
Data Valid
t
ACS
CS
D
OUT
t
CLZ(5)
t
CLZ(5)
PDM4M4110
8-72
Rev 2.3 - 1/15/96
PRELIMINARY
Timing Waveforms of Write Cycle No.1
(1)
Timing Waveforms of Write Cycle No.2
(1,6)
NOTES 1
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to end the write cycle.
4. During this period, I/O pins are in the output state, and input signals to the opposite phase to the outputs must not
be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-
impedance state.
6.
OE
is continuously LOW (
OE
= V
IL
)
7. D
OUT
is the same phase of write data of this write cycle.
8. If
CS
is LOW during this period, I/O pins are in the output state. Then the data input signals of the opposite phase
to the outputs must not be applied to them.
9. Transition is measured
200 mV for steady state with a 5 pF load (including scope and jig). This parameter is deter-
mined by device characteristics but is not production tested.
t
AW
CS
D
OUT
t
AS
t
WR
t
WC
t
WP(2)
t
WHZ(6)
t
OHZ(4,9)
t
DH
t
DW
D
IN
WE
OE
ADDRESS
t
AW
CS
D
OUT
t
AS
t
WC
t
WP(2)
t
WHZ(4,9)
t
OW(9)
t
OH
t
DH
t
DW
D
IN
WE
ADDRESS
(8)
t
WR(3)
(7)
t
CW
(5)
PDM4M4110
Rev 2.3 - 1/15/96
8-73
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PRELIMINARY
Package Dimensions
SIMM Version
ZIP Version
3.950
0.600
PIN 1
FRONT VIEW
0.250
0.100
SIDE VIEW
0.050
0.125
0.100
0.020
0.250
BACK VIEW
PIN 1
4.250
0.650
PIN 1
FRONT VIEW
BACK VIEW
0.250
0.050
SIDE VIEW
0.250
0.050
0.400
3.984
0.250
PIN 1
0.080
PDM4M4110
8-74
Rev 2.3 - 1/15/96
PRELIMINARY
Ordering Information
PDM4M XXXXX S XX X X
Device Power Speed Package Temp
Blank
Commercial (0 to 70C)
Z
M
72-pin ZIP
72-pin SIMM
15
20
25
35
Commercial
S
Standard Power
4110
512K x 32
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