ChipFind - документация

Электронный компонент: PDM41532

Скачать:  PDF   ZIP

Document Outline

Rev. 1.3 - 4/10/98
1
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
Description
The PDM41532 is a high-performance CMOS static
RAM organized as 65,536 x 16 bits. The PDM41532
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM41532 operates from a single 5.0V power
supply and all inputs and outputs are fully TTL-
compatible. The PDM41532 comes in two versions,
the standard power version PDM41532SA and a low
power version PDM41532LA. The two versions are
functionally the same and only differ in their power
consumption.
The PDM41532 is available in a 44-pin 400 mil plas-
tic SOJ and a 44-pin plastic TSOP (II) package
suitable for high-density surface assembly and is
suitable for use in high-speed applications such as
cache memory and high-speed storage.
PDM41532
64K x 16 CMOS
Static RAM
A8-A0
Memory
Cell
Array
256 x 128 x 32
Row Address
Buffer
Control
Logic
Sense Amp
Column
Decoder
Column
Address
Buffer
Row Decoder
Clock
Generator
A15-A9
CE
LB
UB
OE
WE
Data
Input/
Output
Buffer
Vcc
Vss
I/O15-I/O0
Features
n
High-speed access times
- Com'l: 10, 12, 15 and 20 ns
- Ind: 12, 15 and 20 ns
n
Low power operation (typical)
- PDM41532SA
Active: 350 mW
Standby: 50 mW
- PDM41532LA
Active: 300 mW
Standby: 25mW
n
High-density 64K x 16 architecture
n
Single +5V (
10%) power supply
n
Fully static operation
n
TTL-compatible inputs and outputs
n
Output buffer controls: OE
n
Data byte controls: LB, UB
n
Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
PDM41532
2
Rev. 1.3 - 4/10/98
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
15
16
29
30
31
32
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
13
14
33
34
35
36
37
38
39
40
41
42
43
44
19
20
21
22
17
18
23
24
25
26
27
28
Pin Description
Name
Description
A15-A0
Address Inputs
I/O15-I/O0
Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
LB, UB
Data Byte Control Inputs
NC
No connect
V
SS
Ground
V
CC
Power (+5V)
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
15
16
29
30
31
32
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
13
14
33
34
35
36
37
38
39
40
41
42
43
44
19
20
21
22
17
18
23
24
25
26
27
28
SOJ
TSOP (II)
Capacitance
(T
A
= +25
C, f = 1.0 MHz)
NOTE: 1. This parameter is determined by device characterization, but is not production tested.
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= V
SS
6
pF
C
I/O
Output Capacitance
V
I/O
= V
SS
8
pF
PDM41532
Rev. 1.3 - 4/10/98
3
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
Operating Mode
NOTE: 1. H = V
IH
, L = V
IL
, X = DON'T CARE
Mode
CE
OE
WE
LB
UB
I/O7-I/O0
I/O15-I/O8
Power
Read
L
L
H
L
L
Output
Output
I
CC
H
L
High Impedance
Output
I
CC
L
H
Output
High Impedance
I
CC
Write
L
X
L
L
L
Input
Input
I
CC
H
L
High Impedance
Input
I
CC
L
H
Input
High Impedance
I
CC
Output Disable
L
H
H
X
x
High Impedance
High Impedance
I
CC
L
X
X
H
H
High Impedance
High Impedance
I
CC
Standby
H
X
X
X
X
High Impedance
High Impedance
I
SB
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
ja
the thermal resistance of the package. For
this product, use the following
ja
values:
SOJ: 59
o
C/W
TSOP: 87
o
C/W
Symbol
Rating
Com'l.
Ind.
Unit
V
TERM
Terminal Voltage with Respect to V
SS
0.5 to +7.0
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
55 to +125
65 to +135
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
1.5
1.5
W
I
OUT
DC Output Current
50
50
mA
T
j
Maximum Junction Temperature
(2)
125
145
C
PDM41532
4
Rev. 1.3 - 4/10/98
PRELIMINARY
Recommended DC Operating Conditions
DC Electrical Characteristics
(V
CC
= 5.0V
10%)
NOTE:1.V
IL
(min) = 3.0V for pulse width less than 20 ns.
Power Supply Characteristics
NOTES: All values are maximum guaranteed values.
Symbol
Description
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
V
SS
Supply Voltage
0
0
0
V
Industrial
Ambient Temperature
40
25
85
C
Commercial
Ambient Temperature
0
25
70
C
PDM41532SA
PDM41532LA
Unit
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
I
LI
Input Leakage Current
V
CC
= Max., V
IN
= Vss to V
CC
5
5
5
5
A
I
LO
Output Leakage Current
V
CC
= Max.,
CE = V
IH
, V
OUT
= Vss to V
CC
5
5
5
5
A
V
IL
Input Low Voltage
0.5
(1)
0.8
0.5
(1)
0.8
V
V
IH
Input High Voltage
2.2
Vcc +
0.5
2.2
Vcc +
0.5
V
V
OL
Output Low Voltage
I
OL
= 8 mA, V
CC
= Min.
--
0.4
--
0.4
V
V
OH
Output High Voltage
I
OH
= 4 mA, V
CC
= Min.
2.4
--
2.4
--
V
-10
-12
-15
-20
Symbol Parameter
Power
Com'l.
Com'l
Ind.
Com'l
Ind.
Com'l
Ind.
Unit
I
CC
Operating Current
CE = V
IL
SA
300
280
290
260
270
240
250
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
LA
150
140
150
130
140
120
130
mA
I
SB
Standby Current
CE = V
IH
SA
40
40
40
35
35
30
30
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
LA
30
30
30
25
25
20
20
mA
I
SB1
Full Standby Current
CE
V
CC
0.2V
SA
10
10
15
10
15
10
15
mA
f = 0
V
CC
= Max.,
V
IN
V
CC
0.2V or
0.2V
LA
5
5
10
5
10
5
10
mA
PDM41532
Rev. 1.3 - 4/10/98
5
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
AC Test Conditions
Input pulse levels
V
SS
to 3.0V
Input rise and fall times
3 ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
+5V
480
255
D
OUT
30 pF
+5V
480
255
D
OUT
5 pF
Figure 1.Output Load
Figure 2.Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
, t
HZOE
,
t
LZBE
, t
HZBE
)
PDM41532
6
Rev. 1.3 - 4/10/98
PRELIMINARY
AC Electrical Characteristics
NOTES: 1. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
.
2. t
HZCE
, t
HZOE
, and t
HZWE
are specified with C
L
= 5 pF as in Figure 2. Transition is measured
200 mV from
steady state voltage.
Description
10
12
15
20
READ Cycle
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
READ cycle time
t
RC
10
--
12
--
15
--
20
--
ns
Address access time
t
AA
--
10
--
12
--
15
--
20
ns
Chip enable access time
t
ACE
--
9
--
11
--
14
--
18
ns
Byte access time
t
BA
--
5
--
6
--
7
--
9
ns
Output hold from address change
t
OH
2
--
2
--
3
--
3
--
ns
Byte disable to output in low-Z
(1, 6)
t
LZBE
0
--
0
--
0
--
0
--
ns
Byte enable to output in high-Z
(1, 6)
t
HZBE
--
5
--
6
--
7
--
9
ns
Chip enable to output in low-Z
(1, 6)
t
LZCE
3
--
3
--
3
--
3
--
ns
Chip disable to output high-Z
(1, 6)
t
HZCE
--
5
--
6
--
7
--
9
ns
Output enable access time
t
AOE
--
5
--
6
--
7
--
9
ns
Output enable to output in low-Z
(1, 6)
t
LZOE
0
--
0
--
0
--
0
--
ns
Output disable to output in high-Z
(1, 6)
t
HZOE
--
5
--
6
--
7
--
9
ns
t
AA
t
RC
UB, LB
OE
CE
ADDRESSES
t
OH
t
AOE
t
BA
D
OUT
Output Data Valid
t
LZBE(6)
t
LZOE(6)
t
LZCE(6)
t
ACE
t
HZCE(6)
t
HZOE(6)
t
HZBE(6)
Read Cycle Timing Diagram
PDM41532
Rev. 1.3 - 4/10/98
7
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
Write Cycle 1 Timing Diagram
(5)
(WE Controlled)
t
AW
tAS
t
WC
UB, LB
CE
WE
ADDRESSES
t
WP
t
LZWE(6)
t
CW
t
BW
High Impedance
t
HZWE(6)
t
AH
t
DH
t
DS
Data Stable
(3)
(4)
D
OUT
D
IN
Write Cycle 2 Timing Diagram
(5)
(CE Controlled)
t
AW
tAS
t
WC
UB, LB
CE
WE
ADDRESSES
t
WP
t
CW
High Impedance
t
DH
t
DS
Data Stable
D
OUT
D
IN
t
AH
t
BW
t
LZBE(6)
t
LZCE(6)
t
HZWE(6)
PDM41532
8
Rev. 1.3 - 4/10/98
PRELIMINARY
AC Electrical Characteristics
Description
-10
-12
-15
-20
WRITE Cycle
Sym
Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE cycle time
t
WC
10
--
12
--
15
--
20
--
ns
Chip enable to end of write
t
CW
9
--
10
--
12
--
12
--
ns
Address valid to end of write
t
AW
9
--
8
--
10
--
12
--
ns
Byte pulse width
t
BW
9
--
8
--
10
--
12
--
ns
Address setup time
t
AS
0
--
0
--
0
--
0
--
ns
Address hold from end of write
t
AH
0
--
0
--
0
--
0
--
ns
Write pulse width
t
WP
9
--
8
--
9
--
10
--
ns
Data setup time
t
DS
5
--
6
--
7
--
9
--
ns
Data hold time
t
DH
0
--
0
--
0
--
0
--
ns
Byte disable to output in low-Z
(1, 5, 6)
t
LZBE
0
--
0
--
0
--
0
--
ns
Byte enable to output in high-Z
(1, 5, 6)
t
HZBE
--
5
--
6
--
7
--
9
ns
Output disable to output in low-Z
(1, 5, 6)
t
LZOE
0
--
0
--
0
--
0
--
ns
Output enable to output in high-Z
(1, 5, 6)
t
HZOE
--
5
--
6
--
7
--
9
ns
Write disable to output in low-Z
(1, 5, 6)
t
LZWE
0
--
0
--
0
--
0
--
ns
Write enable to output in high-Z
(1, 5, 6)
t
HZWE
5
--
6
--
7
--
9
ns
Write Cycle 3 Timing Diagram
(5)
(UB, LB Controlled)
t
AW
tAS
t
WC
UB, LB
CE
WE
ADDRESSES
t
WP
t
CW
High Impedance
t
DH
t
DS
Data Stable
D
OUT
D
IN
t
AH
t
BW
t
LZBE(6)
t
LZCE(6)
t
HZWE(6)
PDM41532
Rev. 1.3 - 4/10/98
9
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DR
V
CC
for Retention Data
2.5
--
5.5
V
I
CCDR
Data Retention Current
CE
V
CC
0.2V
V
IN
V
CC
0.2V
or
0.2V
V
CC
= 2V
--
95
500
A
V
CC
= 3V
--
350
750
A
t
CDR
Chip Deselect to Data Retention Time
0
--
--
ns
t
R
(1)
Operation Recovery Time
t
RC
--
--
ns
NOTES: 1. This parameter is determined by device characterization but is not production tested.
2. WE is HIGH for read cycles.
3. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high imped-
ance state.
4. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high imped-
ance state.
5. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period.
6. Measured with C
L
= 5pF as in Figure 2. Transition is measured +200mv from steady state voltage.
Low V
CC
Data Retention Waveform
DON'T CARE
VCC
V
V
IH
IL
t
CDR
V
t
R
4.5V
4.5V
Data Retention Mode
CE
DR
VDR
Data Retention Electrical Characteristics (LA Version Only)
NOTE: 1. This parameter is sampled.
PDM41532
10
Rev. 1.3 - 4/10/98
PRELIMINARY
Ordering Information
Device Type
Power
Speed
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Commercial (0
to +70
C)
Industrial (40
C to +85
C)
10
12
15
20
SA
Standard Power
LA
Low Power
Blank
I
A
Automotive ( 40
C to +105
C)
Blank Tubes
TR Tape & Reel
TY Tray
PDM41532 - (64Kx16) Static RAM
XXXXX
X
XX
X
X
X
SO
44-pin 400 mil Plastic SOJ
T
44-pin Plastic TSOP
Commercial Only