Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. 00B
08/01/03
IS23SC4442
ISSI
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
256 BYTE EEPROM
WITH WRITE PROTECT FUNCTION AND
PROGRAMMABLE SECURITY
FEATURES
Standard CMOS process
256 x 8 bits EEPROM organization
Byte-wise addressing
Irreversible byte-wise write protection of lowest
32 address (Byte 0..31)
3-byte Programmable Security Code (PSC) for
memory write/erase protection
2.7-5.5V power supply for read and write/erase
Low power operation: 3 mA typical active current
2.5 ms programming time
2-wire serial interface
End of processing indication
ISO standard 7816 compatible
High reliability:
1,000,000 erase/write cycles guaranteed
10 years data retention
Wide operating temperature range
3
0
o
C to 75
o
C
PRELIMINARY INFORMATION
August 2003
DESCRIPTION
IS23SC4442 contains 256 x 8 bits of EEPROM main
memory and a 32 x 1 bit protection PROM memory.
The main memory can be randomly accessed byte by
byte. During memory erase, all 8 bits of a byte are set
to logical one. During memory write, individual bit(s)
are set to logical zeros depend on the data value to be
written. Normally, a data change may consists of an
erase and a write operation. The write or erase operation
takes at least 2.5 ms to complete.
The first 32 bytes (Address: 0 to 31) in memory are
irreversibly protected by the corresponding 32 protect
bits in the 32 x 1 bit protection memory. The 32 protect
bits are onetime programmable, and they cannot be
erased once they are set to logical zero.
IS23SC4442 provides a 3-bit Error Counter (EC), and
three bytes Programmable Security Code (PSC) to
prevent unauthorized erase/write operation to the
memory. All the memory, except the PSC, can be read
after the chip is powered on. But, the memory can be
written or erased only after the PSC is entered and
verified correct. After three successive unsuccessful
verifications of PSC, the Error Counter locks the chip
from a further attempt, and the memory can never be
erased or written.
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
08/01/03
IS23SC4442
ISSI
PIN CONFIGURATION
Definitions and Functions
Card Contact
Symbol
Description
C1
VCC
Supply Voltage
C2
RST
Reset
C3
CLK
Clock Input
C4
NC
No Connect
C5
GND
Ground
C6
NC
No Connect
C7
I/O
Bidirectional Data I/O (Open drain)
C8
NC
No Connect
Note:
An external pull up resistor is needed to be connected to the I/O pin.
C1
C2
C3
C4
C5
C6
C7
C8
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. 00B
08/01/03
IS23SC4442
ISSI
MEMORY OVERVIEW
Reset,
Blockade
Logic
Interface
Sequencer
and
Security
Logic
High-Volt
Generator
Protection
Memory
(PROM)
Decoder
224 Byte
Unprotected
Data Memory
32 Byte
Protectable
Data Memory
Manufacturer
Code
225
32
31
0
Main
Memory
VCC
RST
CLK
I/O
GND
Functional Description
The IS23SC4442 works on a 2-wire serial transmission
protocol. Data is input or output from the chip through
the I/O pin at the falling edge of CLK. The following are
the four modes of operations:
Reset and Answer-to-Reset
Command Mode
Outgoing Data Mode
Processing Mode
Reset and Answer-to-Reset
The Answer-to-Reset operation conforms to ISO 7816-3
ATR standard. The reset action can be invoked at any
time during the operation to terminate any active com-
mand operation. With RST High, the internal address
counter is set to zero by the CLK pulse. The LSB of the
first byte data in the memory will be output from I/O when
RST goes from High to Low. By continuing to send
pluses to CLK, the contents of the first four bytes will be
output from I/O pin. After the ATR process completes,
the I/O pin will be set to high impedance.
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00B
08/01/03
IS23SC4442
ISSI
FUNCTIONAL DESCRIPTION
Block Diagram
EEPROM
256X8
Erase with
write
protection
Main memory
255
32
31
0
31
0
Protection memory
Security memory
Reference data
Reference data
Reference data
EC
3
2
1
0
PSC
8
5
High-voltage
generator Bias
current generator
Vecoder
Column
sampling
Addr. & data
register
comparator
Programming
Control
Reset
Timing
security
Interface
memory
addr.
data
addr.
addr.
data
data
2LSB
VCC
GND
I/O
RST
CLK
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. 00B
08/01/03
IS23SC4442
ISSI
Functional Description
The IS23SC4442 contains 256 bytes of EEPROM main
memory (see block diagram) and a 32 bit protection
memory. The main memory is byte-wise erased and
written. When the memory is erased, 8 bits of the data
byte are all set to logic 1. When the memory is written, a
data byte can be programmed bit by bit, and it is set to
logic 0 according to the logic between the old and new
data. Generally, updating data includes an erase and
write procedure. When updated, new input data and the
contents of the old data are compared. If none of the 8
bits requires a logic 0 to 1 change, the erase operation
will be skipped. On the contrary, the write operation will
be skipped if no logic 1 to 0 change is necessary. The
write and erase operation takes at least 2.5 ms each.
The first 32 bytes can be protected individually by writing
the corresponding bit in the protection memory. Each
data byte in the address range and its assigned bit in the
protection memory have the same address. Once the
protection bit is written it cannot be erased.
The security memory of IS23SC4442 contains an error
counter (bit 0-bit 2) and 3 bytes reference data. The three
bytes reference data are as a whole called programmable
security code (PSC). After power on, except for the
PSC, the whole memory can always be read. The error
counter can always be written. After three successive
unsuccessful PSC verifications, the error counter will
block the chip, and write and erase operation to the
memory will be forbidden.
TRANSMISSION PROTOCOL
Transmission Mode
The transmission protocol is a two-wire link protocol
between the interface device IFD and IC. The protocol
type is "S = 10". All data changes on I/O are triggered by
the falling edge on CLK.
The transmission protocol is composed of the following
four modes:
Reset and answer- to-reset
Command mode
Data output mode
Processing mode
Reset and Answer-To-Reset
According to IS07816-3, Answer-To-Reset takes place
during operation. The reset can be implemented at any
time. During reset, the address counter is set to zero.
When RST is set from high level to low level, the lowest
bit of the first byte is read on the I/O. Under continuous
31 clock pulses, the contents of the first 4 byte EEPROM
addresses can be read out. The 33rd clock pulse sets
the I/O to high impedance. During Answer-To-Reset, any
start and stop condition is ignored.
Figure: Reset and Answer-To-Reset
1
2
3
31
32
1
2
3
31
32
IC sets I/O high
impedance
V
cc
RST
CLK
I/O
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