IS42S32400B
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
PRELIMINARY INFORMATION, Rev. 00F
03/30/06
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
ISSI
FEATURES
Clock frequency: 167, 143, 125, 100 MHz
Fully synchronous; all signals referenced to a
positive clock edge
Internal bank for hiding row access/precharge
Power supply
V
DD
V
DDQ
IS42S32400B
3.3V
3.3V
LVTTL interface
Programmable burst length
(1, 2, 4, 8, full page)
Programmable burst sequence:
Sequential/Interleave
Auto Refresh (CBR)
Self Refresh with programmable refresh periods
4096 refresh cycles every 64 ms
Random column address every clock cycle
Programmable
CAS latency (2, 3 clocks)
Burst read/write and burst read/single write
operations capability
Burst termination by burst stop and precharge
command
Available in Industrial Temperature
Available in 86-pin TSOP-II and 90-ball FBGA
Available in Lead-free
OVERVIEW
ISSI
's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4
Banks.
4Meg x 32
128-MBIT SYNCHRONOUS DRAM
PRELIMINARY INFORMATION
APRIL 2006
KEY TIMING PARAMETERS
Parameter
-6
-7
Unit
Clk Cycle Time
CAS Latency = 3
6
7
ns
CAS Latency = 2
8
10
ns
Clk Frequency
CAS Latency = 3
167
143
Mhz
CAS Latency = 2
125
100
Mhz
Access Time from Clock
CAS Latency = 3
5.4
5.4
ns
CAS Latency = 2
6.5
6.5
ns
ISSI
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00F
03/30/06
IS42S32400B
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
DD
and 3.3V V
DDQ
memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 256 columns by 32 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
CLK
CKE
CS
RAS
CAS
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A10
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MUL
TIPLEXER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQM0 - DQM3
DQ 0-31
V
DD
/V
DDQ
Vss/Vss
Q
12
12
8
12
12
8
32
32
32
32
256
(x 32)
4096
4096
4096
R
O
W DECODER
4096
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROW
ADDRESS
BUFFER
A11
4
FUNCTIONAL BLOCK DIAGRAM (FOR 1MX32X4 BANKS)
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
PRELIMINARY INFORMATION
Rev. 00F
03/30/06
ISSI
IS42S32400B
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
PIN DESCRIPTIONS
A0-A11
Row Address Input
A0-A7
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ31
Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
A11
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
WE
Write Enable
DQM0-DQM3
x32 Input/Output Mask
V
DD
Power
Vss
Ground
V
DDQ
Power Supply for I/O Pin
Vss
Q
Ground for I/O Pin
NC
No Connection
ISSI
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00F
03/30/06
IS42S32400B
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
VDDQ
VDD
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
VSSQ
DQ0
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
PIN DESCRIPTIONS
A0-A11
Row Address Input
A0-A7
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ31
Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE
Write Enable
DQM0-DQM3
x32 Input/Output Mask
V
DD
Power
Vss
Ground
V
DDQ
Power Supply for I/O Pin
Vss
Q
Ground for I/O Pin
NC
No Connection
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
PRELIMINARY INFORMATION
Rev. 00F
03/30/06
ISSI
IS42S32400B
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A11
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address A0-
A7), with A10 defining auto precharge) to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
BA0, BA1
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS
Input Pin
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
CS
Input Pin
The
CS input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when
CS is HIGH.
DQM0-DQM3
Input Pin
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buffer
byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance
state whenDQMn is HIGH. This function corresponds to
OE in conventional DRAMs. In
write mode, DQMn control the input buffer. When DQMn is LOW, the corresponding
buffer byte is enabled, and data can be written to the device. When DQMn is HIGH,
input data is masked and cannot be written to the device.
DQ0-DQ31
Input/Output Pin
Data on the Data Bus is latched on these pins during Write commands, and buffered
after Read commands.
RAS
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
V
DDQ
Power Supply Pin
V
DDQ
is the output buffer power supply.
V
DD
Power Supply Pin
V
DD
is the device internal power supply.
V
SSQ
Power Supply Pin
V
SSQ
is the output buffer ground.
V
SS
Power Supply Pin
V
SS
is the device internal ground.
PDF 
ZIP