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1
05/28/04
IRF3707ZPbF
IRF3707ZSPbF
IRF3707ZLPbF
HEXFET
Power MOSFET
Notes
through
are on page 12
Applications
Benefits
l
Low R
DS(on)
at 4.5V V
GS
l
Ultra-Low Gate Impedance
l
Fully Characterized Avalanche Voltage
and Current
l
High Frequency Synchronous Buck
Converters for Computer Processor Power
l
Lead-Free
D
2
Pak
IRF3707ZS
TO-220AB
IRF3707Z
TO-262
IRF3707ZL
Absolute Maximum Ratings
Parameter
Units
V
DS
Drain-to-Source Voltage
V
V
GS
Gate-to-Source Voltage
I
D
@ T
C
= 25C
Continuous Drain Current, V
GS
@ 10V
g
A
I
D
@ T
C
= 100C
Continuous Drain Current, V
GS
@ 10V
g
I
DM
Pulsed Drain Current
P
D
@T
C
= 25C
Maximum Power Dissipation
W
P
D
@T
C
= 100C
Maximum Power Dissipation
Linear Derating Factor
W/C
T
J
Operating Junction and
C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
2.653
C/W
R
CS
Case-to-Sink, Flat Greased Surface
e
0.50
R
JA
Junction-to-Ambient
e
62
R
JA
Junction-to-Ambient (PCB Mount)
h
40
57
0.38
28
Max.
59
i
42
i
230
20
30
300 (1.6mm from case)
-55 to + 175
10 lbf
x
in (1.1 N
x
m)
V
DSS
R
DS(on)
max
Qg
30V
9.5m
:
9.7nC
PD - 95333
IRF3707Z/S/LPbF
2
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S
D
G
Static @ T
J
= 25C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BV
DSS
Drain-to-Source Breakdown Voltage
30
V
V
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
0.023
mV/C
R
DS(on)
Static Drain-to-Source On-Resistance
7.5
9.5
m
10
12.5
V
GS(th)
Gate Threshold Voltage
1.35
1.80
2.25
V
V
GS(th)
/
T
J
Gate Threshold Voltage Coefficient
-5.3
mV/C
I
DSS
Drain-to-Source Leakage Current
1.0
A
150
I
GSS
Gate-to-Source Forward Leakage
100
nA
Gate-to-Source Reverse Leakage
-100
gfs
Forward Transconductance
81
S
Q
g
Total Gate Charge
9.7
15
Q
gs1
Pre-Vth Gate-to-Source Charge
2.8
Q
gs2
Post-Vth Gate-to-Source Charge
1.0
nC
Q
gd
Gate-to-Drain Charge
3.4
Q
godr
Gate Charge Overdrive
2.5
See Fig. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
4.4
Q
oss
Output Charge
6.2
nC
t
d(on)
Turn-On Delay Time
9.8
t
r
Rise Time
41
t
d(off)
Turn-Off Delay Time
12
ns
t
f
Fall Time
3.6
C
iss
Input Capacitance
1210
C
oss
Output Capacitance
260
pF
C
rss
Reverse Transfer Capacitance
130
Avalanche Characteristics
Parameter
Units
E
AS
Single Pulse Avalanche Energy
d
mJ
I
AR
Avalanche Current
A
E
AR
Repetitive Avalanche Energy
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
59
i
(Body Diode)
A
I
SM
Pulsed Source Current
230
(Body Diode)
V
SD
Diode Forward Voltage
1.0
V
t
rr
Reverse Recovery Time
14
21
ns
Q
rr
Reverse Recovery Charge
5.2
7.8
nC
MOSFET symbol
V
GS
= 4.5V, I
D
= 17A
e
V
GS
= 4.5V
Typ.
I
D
= 17A
V
GS
= 0V
V
DS
= 15V
T
J
= 25C, I
F
= 17A, V
DD
= 15V
di/dt = 100A/s
e
T
J
= 25C, I
S
= 17A, V
GS
= 0V
e
showing the
integral reverse
p-n junction diode.
V
DS
= V
GS
, I
D
= 250A
V
DS
= 24V, V
GS
= 0V
V
DS
= 24V, V
GS
= 0V, T
J
= 125C
Clamped Inductive Load
V
DS
= 15V, I
D
= 17A
V
DS
= 16V, V
GS
= 0V
V
DD
= 15V, V
GS
= 4.5V
e
I
D
= 17A
V
DS
= 15V
Conditions
V
GS
= 0V, I
D
= 250A
Reference to 25C, I
D
= 1mA
V
GS
= 10V, I
D
= 21A
e
V
GS
= 20V
V
GS
= -20V
Conditions
5.7
Max.
40
23
= 1.0MHz
IRF3707Z/S/LPbF
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3
Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
VGS
TOP
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM
3.0V
30s PULSE WIDTH
Tj = 25C
3.0V
0.1
1
10
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
30s PULSE WIDTH
Tj = 175C
30V
VGS
TOP
10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM
3.0V
2
3
4
5
6
7
8
VGS, Gate-to-Source Voltage (V)
10.0
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
)
TJ = 25C
TJ = 175C
VDS = 10V
30s PULSE WIDTH
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (C)
0.5
1.0
1.5
2.0
R
D
S
(
o
n
)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
N
o
r
m
a
l
i
z
e
d
)
ID = 42A
VGS = 10V
IRF3707Z/S/LPbF
4
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.0
0.5
1.0
1.5
2.0
VSD, Source-to-Drain Voltage (V)
0.01
0.10
1.00
10.00
100.00
1000.00
I S
D
,
R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
TJ = 25C
TJ = 175C
VGS = 0V
0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100sec
Tc = 25C
Tj = 175C
Single Pulse
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
100000
C
,
C
a
p
a
c
i
t
a
n
c
e
(
p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
2
4
6
8
10
12
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V
G
S
,
G
a
t
e
-
t
o
-
S
o
u
r
c
e
V
o
l
t
a
g
e
(
V
)
VDS= 24V
VDS= 15V
ID= 17A
IRF3707Z/S/LPbF
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5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
25
50
75
100
125
150
175
TC , Case Temperature (C)
0
10
20
30
40
50
60
I D
,
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
Limited By Package
-75 -50 -25
0
25
50
75 100 125 150 175 200
TJ , Temperature ( C )
0.5
1.0
1.5
2.0
2.5
V
G
S
(
t
h
)
G
a
t
e
t
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
ID = 250A
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
(
Z
t
h
J
C
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (C/W)
i (sec)
1.163 0.000257
1.073 0.001040
0.419 0.003089
J
J
1
1
2
2
3
3
R
1
R
1
R
2
R
2
R
3
R
3
C
Ci=
i
/
Ri
Ci=
i
/
Ri
IRF3707Z/S/LPbF
6
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D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
F
50K
.2
F
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
RG
IAS
0.01
tp
D.U.T
L
VDS
+
-
VDD
DRIVER
A
15V
20V
V
GS
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
V
GS
Pulse Width < 1s
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (C)
0
25
50
75
100
125
150
175
E
A
S
,
S
i
n
g
l
e
P
u
l
s
e
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
ID
TOP 4.5A
6.8A
BOTTOM 23A
IRF3707Z/S/LPbF
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7
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
5%
Body Diode
Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
IRF3707Z/S/LPbF
8
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on)
of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
P
loss
= I
rms
2
R
ds(on )
(
)
+ I
Q
gd
i
g
V
in
f
+ I
Q
gs 2
i
g
V
in
f
+ Q
g
V
g
f
(
)
+
Q
oss
2
V
in
f
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 16.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to I
dmax
at which time the drain voltage be-
gins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q
oss
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances C
ds
and C
dg
when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss
= P
conduction
+ P
drive
+ P
output
*
P
loss
= I
rms
2
R
ds(on)
(
)
+ Q
g
V
g
f
(
)
+
Q
oss
2
V
in
f
+ Q
rr
V
in
f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs' susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Q
oss
Characteristic
IRF3707Z/S/LPbF
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9
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.32 (.052)
1.22 (.048)
3X
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
4.69 (.185)
4.20 (.165)
3X
0.93 (.037)
0.69 (.027)
4.06 (.160)
3.55 (.140)
1.15 (.045)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
3X
1.40 (.055)
1.15 (.045)
2.54 (.100)
2X
0.36 (.014) M B A M
4
1 2 3
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
HEXFET
1- GATE
2- DRAIN
3- SOURCE
4- DRAIN
LEAD ASSIGNMENTS
IGBTs, CoPACK
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
E XAMPL E :
IN T HE AS S E MB L Y L INE "C"
T HIS IS AN IR F 1010
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997
PAR T NU MB E R
AS S E MB L Y
L OT CODE
DAT E CODE
YE AR 7 = 1997
L INE C
WE E K 19
L OGO
R E CT IF IE R
INT E R NAT IONAL
Note: "P" in assembly line
position indicates "Lead-Free"
IRF3707Z/S/LPbF
10
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D
2
Pak Part Marking Information
D
2
Pak Package Outline
Dimensions are shown in millimeters (inches)
Note: "P" in as s embly line
pos ition indicates "L ead-F ree"
F 530S
T HIS IS AN IR F 530S WIT H
L OT CODE 8024
AS S E MB L E D ON WW 02, 2000
IN T H E AS S E MB L Y L INE "L "
AS S E MB L Y
L OT CODE
INT E R NAT IONAL
R E CT IF IE R
L OGO
PAR T NU MB E R
DAT E CODE
YE AR 0 = 2000
WE E K 02
L INE L
OR
F 530S
A = AS S E MB L Y S IT E CODE
WE E K 02
P = DE S IGNAT E S L E AD-F R E E
PR ODU CT (OPT IONAL )
R E CT IF IE R
INT E R NAT IONAL
L OGO
LOT CODE
AS S E MB L Y
YE AR 0 = 2000
DAT E CODE
PAR T NU MB E R
IRF3707Z/S/LPbF
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11
TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
AS S E MBL Y
L OT CODE
RE CT IF IE R
INT E RNAT IONAL
AS S E MB L E D ON WW 19, 1997
Note: "P" in as s embly line
pos ition indicates "Lead-F ree"
IN T HE AS S E MB L Y L INE "C"
L OGO
T HIS IS AN IRL 3103L
L OT CODE 1789
E XAMPLE :
LINE C
DAT E CODE
WE E K 19
YE AR 7 = 1997
PART NU MBE R
PART NUMB E R
L OGO
L OT CODE
AS S EMB L Y
INT E RNAT IONAL
RE CT IF IER
PRODUCT (OPT IONAL)
P = DE S IGNAT E S LE AD-F REE
A = AS S E MB L Y S IT E CODE
WE E K 19
YE AR 7 = 1997
DAT E CODE
OR
IRF3707Z/S/LPbF
12
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 05/04
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting T
J
= 25C, L = 0.15mH, R
G
= 25
,
I
AS
= 23A.
Pulse width
400s; duty cycle
2%.
C
oss
eff. is a fixed capacitance that gives the same
charging time as C
oss
while V
DS
is rising from 0 to
80% V
DSS
.
This is only applied to TO-220AB pakcage.
This is applied to D
2
Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 42A.
TO-220AB package is not recommended for Surface Mount Application.
D
2
Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449)
15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
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