1
File Number 3088.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
ICL7149
3-3/4 Digit, Autoranging Multimeter
The Intersil ICL7149 is a high performance, low power,
autoranging digital multimeter lC. Unlike other autoranging
multimeter ICs, the ICL7149 always displays the result of a
conversion on the correct range. There is no "range hunting"
noticeable in the display. The unit will autorange between
the four different ranges. A manual switch is used to select
the 2 high group ranges. DC current ranges are 4mA and
40mA in the low current group, and 400mA and 4A in the
high current group. Resistance measurements are made on
4 ranges, which are divided into two groups. The low
resistance ranges are 4/40k
. The high resistance ranges
are 0.4/4M
. Resolution on the lowest range is 1.
Pinout
ICL7149 (MQFP)
TOP VIEW
Features
18 Ranges
- 4 DC Voltage 400mV, 4V, 40V, 400V
- 2 AC Voltage with Optional AC Circuit
- 4 DC Current 4mA, 40mA, 400mA, 4A
- 4 AC Current with Optional AC Circuit
- 4 Resistance 4k
, 40k, 400k, 4M
Autoranging - First Reading is Always on Correct Range
On-Chip Duplex LCD Display Drive Including Three
Decimal Points and 11 Annunciators
No Additional Active Components Required
Low Power Dissipation - Less than 20mW - 1000 Hour
Typical Battery Life
Display Hold Input
Continuity Output Drives Piezoelectric Beeper
Low Battery Annunciator with On-Chip Detection
Guaranteed Zero Reading for 0V Input on All Ranges
Related Literature
Technical Brief TB363 "Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)"
Functional Block Diagram
Part Number Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
ICL7149CM44
0 to 70
44 Ld MQFP
Q44.10x10
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
28
27
26
25
24
23
22
21
20
19
18
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
M
/A
/A
k/m
OSC IN
OSC OUT
HOLD
BEEPER OUT
mA/
A
/V/A
HI
-DC/LO-AC
NC
ADG
3
/E
3
B
3
/C
3
F
2
/DP
3
G
2
/E
2
A
2
/D
2
POL/AC
NC
BP2
BP1
V+
NC
V-
V
RE
F
LO
HI
DE
I
N
T
CO
M
M
O
N
IN
T
I
IN
T
V
/
TR
I
P
LE
P
O
I
N
T
C
AZ
C
IN
T
B
2
/C
2
F
1
/D
P
2
G
1
/E
1
A
1
/D
1
B
1
/C
1
F
0
/D
P
1
G
0
/E
0
A
0
/D
0
B
0
/C
0
NC
LO
B
A
T/
V
ANALOG SECTION
ANALOG SWITCHES,
AND COMPARATOR
POWER
SUPPLY
SECTION
BEEPER
DRIVER
OSC
COUNTERS
DISPLAY
DIGITAL
SWITCHES
CRYSTAL
V+ V- COM
PIEZO
ELECTRIC
BEEPER
EXTERNAL
RESISTORS
AND CAPACITORS
INTEGRATION
COMMON
DISPLAY
DRIVER
AND
LATCHES
CONTROL LOGIC
INCLUDING
AUTORANGING
LOGIC
Data Sheet
May 2001
OBSOL
ETE PR
ODUCT
NO REC
OMMEN
DED RE
PLACE
MENT
2
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Reference Input Voltage (V
REF
to COM) . . . . . . . . . . . . . . . . . . .3V
Analog Input Current (IN + Current or IN + Voltage) . . . . . . . .100
A
Clock Input Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ to V+ -3
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
V+ = 9V, T
A
= 25
o
C, V
REF
adjusted for -3.700 reading on DC volts, test circuit as shown in Figure 3. Crystal =
120kHz. (See Figure 13)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Zero Input Reading
V
IN
or I
IN
or R
IN
= 0.00
-00.0
-
+00.0
V, I,
Linearity (Best Straight Line) (Note 6)
(Note 1)
-1
-
+1
Counts
Accuracy DC V, 400V Range Only
(Notes 1 and 7)
-
-
1
% of RDG
1
Accuracy DC V, 400V Range Excluded
(Notes 1 and 7)
-
-
0.30
% of RDG
1
Accuracy
, 4K and 400K Range
(Notes 1 and 7)
-
-
0.75
% of RDG
8
Accuracy
, 4K and 4M Range
(Notes 1 and 7)
-
-
1
% of RDG
9
Accuracy DC I, Unadjusted for Full Scale
(Notes 1 and 7)
-
-
0.75
% of RDG
1
Accuracy DC I, Adjusted for Full Scale
(Notes 1 and 7)
-
0.2
-
% of RDG
1
Accuracy AC V
At 60Hz (Notes 5 and 7)
-
2
-
% of RDG
Open Circuit Voltage for
Measurements
R
UNKNOWN
= Infinity
-
V
REF
-
V
Noise V
IN
= 0, DC V (Note 2, 95% of Time)
-
0.1
-
LSB
Noise
V
IN
= 0, AC V (Note 2, 95% of Time)
-
4
-
LSB
Supply Current
V
IN
= 0, DC Voltage Range
-
1.5
2.4
mA
Analog Common (with Respect to V+)
I
COMMON
< 10
A
2.7
2.9
3.1
V
Temperature Coefficient of Analog Common
I
COMMON
< 10
A, Temp. = 0
o
C To 70
o
C
-
-100
-
ppm/
o
C
Output Impedance of Analog Common
I
COMMON
< 10
A
-
1
10
Backplane/Segment Drive Voltage
Average DC < 50mV
2.8
3.0
3.2
V
Backplane/Segment Display Frequency
-
75
-
Hz
Switch Input Current
V
IN
= V+ to V- (Note 3)
-50
-
+50
A
Switch Input Levels (High Trip Point)
V+ - 0.5
-
V+
V
Switch Input Levels (Mid Trip Point)
V- + 3
-
V+ - 2.5
V
Switch Input Levels (Low Trip Point)
V-
-
V- + 0.5
V
Beeper Output Drive (Rise or Fall Time)
C
LOAD
= 10nF
-
25
100
s
Beeper Output Frequency
-
2
-
kHz
Continuity Detect
Range = Low
, V
REF
= 1.00V
-
1.5
-
k
Power Supply Functional Operation
V+ to V-
7
9
11
V
Low Battery Detect
V+ to V- (Note 4)
6.5
7
7.5
V
NOTES:
1. Accuracy is defined as the worst case deviation from ideal input value including: offset, linearity, and rollover error.
2. Noise is defined as the width of the uncertainty window (where the display will flicker) between two adjacent codes.
3. Applies to pins 25-28.
4. Analog Common falls out of regulation when the Low Battery Detect is asserted, however the ICL7149 will continue to
operate correctly with a supply voltage above 7V and below 11V.
5. For 50Hz use a 100kHz crystal.
6. Guaranteed by design, not tested.
7. RDG = Reading.
ICL7149
3
Timing Waveform
Pin Descriptions
FIRST DEINTEGRATE
UNDERRANGE
AUTO ZERO
UNDERRANGE
UNDERRANGE
AUTO ZERO
AUTO ZERO
SECOND AUTO ZERO
FOURTH AUTO ZERO
AUTO ZERO
SECOND INTEGRATE
SECOND DEINTEGRATE
THIRD AUTO ZERO
THIRD INTEGRATE
THIRD DEINTEGRATE
FOURTH INTEGRATE
FOURTH DEINTEGRATE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FIRST AUTO ZERO
FIRST INTEGRATE
FIGURE 1. LINE FREQUENCY CYCLES (1 CYCLE = 1000 INTERNAL CLOCK PULSES = 2000 OSCILLATION CYCLES)
I/O
PIN NUMBER
DESCRIPTION
O
1
Segment Driver A
2
/D
2
O
2
Segment Driver G
2
/E
2
O
3
Segment Driver F
2
/DP
3
O
4
Segment Driver B
3
/C
3
O
5
Segment Driver ADG
3
/E
3
O
6
Segment Driver POL/AC
N/A
7
No Connect (NC)
O
8
Backplane 2
O
9
Backplane 1
I
10
V+
N/A
11
NC
I
12
V-
I
13
Reference Input
O
14
Lo
O
15
Hi
I/O
16
Deintegrate
I/O
17
Analog Common
I
18
Int I
I
19
Int V/
I
20
Triple Point
I
21
Auto Zero Capacitor (C
AZ
)
I
22
Integrate Capacitor (C
INT)
N/A
23
NC
O
24
Beeper Output
I
25
mA/
A
I
26
/V/A
I
27
Hi
DC/Lo AC
I
28
Hold
O
29
Oscillator Out
I
30
Oscillator In
O
31
Segment DRIVER k/ m
O
32
Segment Driver
/A
O
33
Segment Driver M
/A
O
34
Segment Driver Lo Bat/V
N/A
35
NC
O
36
Segment Driver B
0
/C
O
37
Segment Driver A
0
/D
0
O
38
Segment Driver G
0
/E
0
O
39
Segment Driver F
0
/DP
1
O
40
Segment Driver B
1
/C
1
O
41
Segment Driver A
1
/D
1
O
42
Segment Driver G
1
/E
1
O
43
Segment Driver F
1
/DP
2
O
44
Segment Driver B
2
/C
2
NOTE: For segment drivers, segments are listed as (segment for
backplane 1)/(segment for backplane 2). Example: pin 36; segment
B
0
is on backplane 1, segment C
0
is on backplane 2.
I/O
PIN NUMBER
DESCRIPTION
ICL7149
4
Detailed Description
General
The Functional Block Diagram shows the digital section
which includes all control logic, counters, and display
drivers. The digital section is powered by V+ and Digital
Common, which is about 3V below V+. The oscillator is also
in the digital section. Normally 120kHz for rejection of 60Hz
AC interference and 100kHz for rejection of 50Hz AC should
be used. The oscillator output is divided by two to generate
the internal master clock. The analog section contains the
integrator, comparator, reference section, analog buffers,
and several analog switches which are controlled by the
digital logic. The analog section is powered from V+ and V-.
DC Voltage Measurement
Autozero
Only those portions of the analog section which are used during
DC voltage measurements are shown in Figure 3. As shown in
the timing diagram (Figure 1), each measurement starts with an
autozero (AZ) phase. During this phase, the integrator and
comparator are configured as unity gain buffers and their non-
inverting inputs are connected to Common. The output of the
integrator, which is equal to its offset, is stored on C
AZ
- the
autozero capacitor. Similarly, the offset of the comparator is
stored in C
lNT
. The autozero cycle equals 1000 clock cycles
which is one 60Hz line cycle with a 120kHz oscillator, or one
50Hz line cycle with a 100kHz oscillator.
Range 1 Integrate
The ICL7149 performs a full autorange search for each
reading, beginning with range 1. During the range 1 integrate
period, internal switches connect the INT V/
terminal to the
Triple Point (Pin 20). The input signal is integrated for 10 clock
cycles, which are gated out over a period of 1000 clock cycles
to ensure good normal mode rejection of AC line interference.
Range 1 Deintegrate
At the beginning of the deintegrate cycle, the polarity of the
voltage on the integrator capacitor (C
INT
) is checked, and
either the DElNT+ or DElNT- is asserted. The integrator
capacitor C
INT
is then discharged with a current equal to
V
REF
/R
DElNT
. The comparator monitors the voltage on C
INT
.
When the voltage on C
INT
is reduced to zero (actually to the
V
OS
of the comparator), the comparator output switches, and
the current count is latched. If the C
INT
voltage zero-crossing
does not occur before 4000 counts have elapsed, the
overload flag is set. "OL" (overload) is then displayed on the
LCD. If the latched result is between 360 and 3999, the count
is transferred to the output latches and is displayed. When the
count is less than 360, an underrange has occurred, and the
ICL7149 then switches to range 2 - the 40V scale.
LOW
BATT
DIGIT 3
2
1
0
DP3
DP2
DP1
AC
a
b
k
M
c
mAV
A
g
d
e
f
FIGURE 2. DISPLAY SEGMENT NOMENCLATURE
+
-
+
-
+
-
TRIPLE
POINT
C
AZ
C
INT
R
DEINT
AZ
DEINT-
DEINT-
V
REF
INTEGRATOR
COMPARATOR
TO LOGIC SECTION
6.7V
ANALOG
V
IN
R
INTV
INT V/
80
A
C
AZ
C
INT
R
DEINT
AZ
AZ
AZ
COMMON
T
T
DEINT+
DEINT+
V+
V-
T = (INT)(AR)(AZ)
AR = AUTORANGE CHOPPER
AZ = AUTOZERO
INT = INTEGRATE
V
REF
COMMON
FIGURE 3. DETAILED CIRCUIT DIAGRAM FOR DC VOLTAGE MEASUREMENT
ICL7149
5
Range 2
The range 2 measurement begins with an autozero cycle
similar to the one that preceded range 1 integration. Range 2
cycle length however, is one AC line cycle, minus 360 clock
cycles. When performing the range 2 cycle, the signal is
integrated for 100 clock cycles, distributed throughout one line
cycle. This is done to maintain good normal mode rejection.
Range 2 sensitivity is ten times greater than range 1 (100 vs
10 clock cycle integration) and the full scale voltage of range 2
is 40V. The range 2 deintegrate cycle is identical to the range
1 deintegrate cycle, with the result being displayed only for
readings greater than 360 counts. If the reading is below 360
counts, the ICL7149 again asserts the internal underrange
signal and proceeds to range 3.
Range 3
The range 3V or 4V full scale measurement is identical to the
range 2 measurement, except that the input signal is integrated
during the full 1000 clock cycles (one line frequency cycle). The
result is displayed if the reading is greater than 360 counts.
Underrange is asserted, and a range 4 measurement is
performed if the result is below 360 counts.
Range 4
This measurement is similar to the range 1, 2 and 3
measurements, except that the integration period is 10,000
clock cycles (10 line cycles) long. The result of this
measurement is transferred to the output latches and
displayed even if the reading is less than 360.
Autozero
After finding the first range for which the reading is above
360 counts, the display is updated and an autozero cycle is
entered. The length of the autozero cycle is variable which
results in a fixed measurement period of 24,000 clock cycles
(24 line cycles).
DC Current
Figure 4 shows a simplified block diagram of the analog
section of the ICL7149 during DC current measurement. The
DC current measurements are very similar to DC voltage
measurements except: 1) The input voltage is developed by
passing the input current through a 0.1
(HI current ranges),
or 9.9
(LOW current ranges) current sensing resistor; 2)
Only those ranges with 1000 and 10,000 clock cycles of
integration are used; 3) The R
lNT l
resistor is 1M
, rather
than the 10M
value used for the R
lNT V
resistor.
By using the lower value integration resistor, and only the 2
most sensitive ranges, the voltage drop across the current
sensing resistor is 40mV maximum on the 4mA and 400mA
ranges; 400mV maximum on the 40mA and 4A scales. With
some increase in noise, these "burden" voltages can be
reduced by lowering the value of both the current sense
resistors and the R
lNT l
resistor proportionally. The DC
current measurement timing diagram is similar to the DC
voltage measurement timing diagram, except in the DC
current timing diagram, the first and second integrate and
deintegrate phases are skipped.
AC Voltage Measurement
The ICL7149 is designed to be used with an optional AC to
DC voltage converter circuit. It will autorange through two
voltage ranges (400V and 40V), and the AC annunciator is
enabled. A typical averaging AC to DC converter is shown in
Figure 5, while an RMS to DC converter is shown in Figure
6. AC current can also be measured with some simple
modifications to either of the two circuits in Figures 5 and 6.
+
-
+
-
+
-
TRIPLE
POINT
C
AZ
C
INT
R
DEINT
AZ
DEINT-
DEINT-
V
REF
INTEGRATOR
COMPARATOR
TO LOGIC SECTION
6.7V
ANALOG
LOW I
R
INTI
INT I
80
A
C
AZ
C
INT
R
DEINT
AZ
AZ
AZ
COMMON
T
T
DEINT+
DEINT+
V+
V-
T = (INT)(AR)(AZ)
AR = AUTORANGE CHOPPER
AZ = AUTOZERO
INT = INTEGRATE
V
REF
9.9
0.1
HIGH I
I
COMMON
FIGURE 4. DETAILED CIRCUIT DIAGRAM FOR DC CURRENT MEASUREMENT
ICL7149
6
FIGURE 5. AC VOLTAGE MEASUREMENT USING OPTIONAL AVERAGING CIRCUIT
FIGURE 6. AC VOLTAGE MEASUREMENT USING OPTIONAL RMS CONVERTER CIRCUIT
ICL7652
20M
V
IN
100k
50k
V
+
4
11
7
10
5
1
8
2
0.1
F
1.0
F
COM
43.2k
19
FULL
INT V/
ICL7149
COMMON
-
+
20M
0.1
F
V-
ICL7652
V
+
4
11
7
10
5
1
8
2
0.1
F
-
+
0.1
F
V-
100k
5k
SCALE
ADJUST
17
0VAC - 400VAC
0Hz - 1000Hz
AD736
V
+
2
7
3
6
8
4
5
10
F
1
19
INT V/
ICL7149
COMMON
+
+
2.2
F
COM
FULL
10M
V
-
SCALE
ADJUST
4.99k
2.2
F
5k
30k
17
V
+
V
IN
0VAC - 400VAC
50Hz - 1000Hz
+
ICL7149
7
Ratiometric
Measurement
The ratiometric
measurement is performed by first integrating
the voltage across an unknown resistor, R
X
, then effectively
deintegrating the voltage across a known resistor (R
KNOWN1
or R
KNOWN2
of Figure 7). The shunting effect of R
INTV
does
not affect the reading because it cancels exactly between
integration and deintegration. Like the current measurements,
the
measurements are split into two sets of ranges. LO
measurements use a 10k
reference resistor, and the full scale
ranges are 4k
and 40k. HI measurements use a 1M
reference resistor, and the full scale ranges are 0.4M
and
4M
. The measurement phases and timing are the same as
the measurement phases and timing for DC current except: 1)
During the integrate phases the input voltage is the voltage
across the unknown resistor R
X
, and; 2) During the deintegrate
phases, the input voltage is the voltage across the reference
resistor R
KNOWN1
or R
KNOWN2
.
Continuity Indication
When the ICL7149 is in the LO
measurement mode, the
continuity circuit of Figure 8 will be active. When the voltage
across R
X
is less than approximately 100mV, the beeper
output will be on. When R
KNOWN
is 10k
, the beeper output
will be on when R
X
is less than 1k
.
Common Voltage
The analog and digital common voltages of the ICL7149 are
generated by an on-chip resistor/zener/diode combination,
shown in Figure 9. The resistor values are chosen so the
coefficient of the diode voltage cancels the positive
temperature coefficient of the zener voltage. This voltage is
then buffered to provide the analog common and the digital
common voltages. The nominal voltage between V+ and
analog common is 3V. The analog common buffer can sink
about 20mA, or source 0.01mA, with an output impedance of
10
. A pullup resistor to V+ may be used if more sourcing
capability is desired. Analog common may be used to
generate the reference voltage, if desired.
Oscillator
The ICL7149 uses a parallel resonant-type crystal in a
Pierce oscillator configuration, as shown in Figure 10, and
requires no other external components. The crystal
eliminates the need to trim the oscillator frequency. An
external signal may be capacitively coupled in OSC IN, with
a signal level between 0.5V and 3V
P-P
. Because the OSC
+
-
+
-
+
-
TRIPLE
POINT
C
AZ
C
INT
R
DEINT
AZ
INTEGRATOR
COMPARATOR
TO LOGIC SECTION
COMMON
R
INTV
INT V/
C
AZ
C
INT
R
DEINT
AZ
AZ
AZ
T
T
DEINT+
DEINT+
T = INT + DEINT
AZ = AUTOZERO
INT = INTEGRATE
V
REF
LOW
+
-
LOW
LO
HI
R
KNOWN 1
R
KNOWN 2
R
X
FIGURE 7. DETAILED CIRCUIT DIAGRAM FOR RATIOMETRIC
MEASUREMENT
+
-
COM
LO
HI
+
-
+
-
R
KNOWN
V
X
BEEPER
OUTPUT
R
UNKNOWN
V
REF
LO
2kHz
V+
V+
V
X
= 100mV
R
X
FIGURE 8. CONTINUITY BEEPER DRIVE CIRCUIT
+
-
P
+
-
P
0.3V
+
-
LOGIC
SECTION
V+
LO BAT
DIGITAL
COMMON
(INTERNAL)
3.1V
+
+
3V
-
ANALOG
COMMON
(PIN 17)
V-
6.7V
125K
5K
180K
80
A
FIGURE 9. ANALOG AND DIGITAL COMMON VOLTAGE
GENERATOR CIRCUIT
+
-
ICL7149
8
OUT pin is not designed to drive large external loads,
loading on this pin should not exceed a single CMOS input.
The oscillator frequency is internally divided by two to
generate the ICL7149 clock. The frequency should be
120kHz to reject 60Hz AC signals, and 100kHz to reject
50Hz signals.
Display Drivers
Figure 11 shows typical LCD Drive waveforms, RMS ON, and
RMS OFF voltage calculations. Duplex multiplexing is used to
minimize the number of connections between the ICL7149
and the LCD. The LCD has two separate back-planes. Each
drive line can drive two individual segments, one referenced
to each backplane. The ICL7149 drives 3
3
/
4
7-segment digits,
3 decimal points, and 11 annunciators. Annunciators are used
to indicate polarity, low battery condition, and the range in
use. Peak drive voltage across the display is approximately
3V. An LCD with approximately 1.4V
RMS
threshold voltage
should be used. The third voltage level needed for duplex
drive waveforms is generated through an on-chip resistor
string. The DC component of the drive waveforms is
guaranteed to be less than 50mV.
Ternary Input
The
/Volts/Amps logic input is a ternary, or 3-level input.
This input is internally tied to the common voltage through a
high-value resistor, and will go to the middle, or "Volts" state,
when not externally connected. When connected to V-,
approximately 5
A of current flows out of the input. In this
case, the logic level is the "Amps", or low state. When
connected to V+, about 5
A of current flows into the input.
Here, the logic level is the "
", or high state. For other pins,
see Table 2.
Component Selection
For optimum performance while maintaining the low-cost
advantages of the ICL7149, care must be taken when
selecting external components. This section reviews
specifications and performance effects of various external
components.
5M
330K
10pF
5pF
OSC OUT
OSC IN
FIGURE 10. INTERNAL OSCILLATOR CIRCUIT DIAGRAM
TABLE 2. TERNARY INPUTS CONNECTIONS
PIN NUMBER
V+
OPEN OR
COM
V-
25
mA
A
Test
26
V
Amps
27
Hi
/DC
Lo
/AC
Test
28
Hold
Auto
Test
BACKPLANE
SEGMENT ON
SEGMENT OFF
V
SEGMENT ON
V
SEGMENT OFF
V
PEAK
V
PEAK /2
O
V
PEAK
O
V
PEAK
O
2V
PEAK
O
(VOLTAGE ACROSS ON SEGMENT)
(VOLTAGE ACROSS OFF SEGMENT)
-2V
PEAK
V
PEAK
O
-V
PEAK
V+
DCOM
V
PEAK
= 3V
10%
RMS ON
2.37V
RMS OFF
1.06V
V
RMS
5
8
--- V
PEAK
ON
=
V
RMS
5
8
--- V
PEAK
OFF
=
FIGURE 11. DUPLEXED LCD DRIVE WAVEFORMS
ICL7149
9
Integrator Capacitor, C
lNT
As with all dual-slope integrating convertors, the integration
capacitor must have low dielectric absorption to reduce linearity
errors. Polypropylene capacitors add undetectable errors at a
reasonable cost, while polystyrene and polycarbonate may be
used in less critical applications. The ICL7149 is designed to
use a 3.3nF (0.0033
F) C
lNT
with an oscillator frequency of
120kHz and an R
lNTV
of 10M
. With a 100kHz oscillator
frequency (for 50Hz line frequency rejection), C
lNT
and R
INTV
affects the voltage swing of the integrator. Voltage swing should
be as high as possible without saturating the integrator.
Saturation occurs when the integrator output is within 1V of
either V+ or V-. Integrator voltage swing should be about
2V
when using standard component values. For different R
lNTV
and oscillator frequencies the value of C
lNT
can be calculated
from:
Integrator Resistors
The normal values of the R
lNT V
and R
lNT l
resistors are 10M
and 1M
respectively. Though their absolute values are not
critical, unless the value of the current sensing resistors are
trimmed, their ratio should be 10:1, within 0.05%. Some carbon
composition resistors have a large voltage coefficient which will
cause linearity errors on the 400V scale. Also, some carbon
composition resistors are very noisy. The class "A" output of the
integrator begins to have nonlinearities if required to sink more
than 70
A (the sourcing limit is much higher). Because R
lNT V
drives a virtual ground point, the input impedance of the meter
is equal to R
lNT V
.
Deintegration Resistor, R
DElNT
Unlike most dual-slope A/D converters, the ICL7149 uses
different resistors for integration and deintegration. R
DElNT
should normally be the same value as R
lNT V
, and have the
same temperature coefficient. Slight errors in matching may
be corrected by trimming the reference voltage.
Autozero Capacitor, C
AZ
The C
AZ
is charged to the integrator's offset voltage during the
autozero phases, and subtracts that voltage from the input
signal during the integrate phases. The integrator thus appears
to have zero offset voltage. Minimum C
AZ
value is determined
by: 1) Circuit leakages; 2) C
AZ
self-discharge; 3) Charge
injection from the internal autozero switches. To avoid errors,
the C
AZ
voltage change should be less than 1/10 of a count
during the 10,000 count clock cycle integration period for the
400mV range. These requirements set a lower limit of 0.047
F
for C
AZ
but 0.1
F is the preferred value. The upper limit on the
value of C
AZ
is set by the time constant of the autozero loop,
and the 1 line cycle time period allotted to autozero. C
AZ
may
be several 10s of
F before approaching this limit.
The ideal C
AZ
is a low leakage polypropylene or Teflon
capacitor. Other film capacitors such as polyester, polystyrene,
and polycarbonate introduce negligible errors. If a few seconds
of settling time upon power-up is acceptable, the C
AZ
may be a
ceramic capacitor, provided it does not have excessive
leakage.
Ohm Measurement Resistors
Because the ICL7149 uses a ratiometric ohm measurement
technique, the accuracy of ohm
reading is primarily
determined by the absolute accuracy of the R
KNOWN1
and
R
KNOWN2
. These should normally be 10k
and 1M, with
an absolute accuracy of at least 0.5%.
Current Sensing Resistors
The 0.1
and 9.9 current sensing resistors convert the
measured current to a voltage, which is then measured using
R
lNT l
. The two resistors must be closely matched, and the ratio
between R
lNT l
and these two resistors must be accurate -
normally 0.5%. The 0.1
resistor must be capable of handling
the full scale current of 4A, which requires it to dissipate 1.6W.
Continuity Beeper
The Continuity Beeper output is designed to drive a
piezoelectric transducer at 2kHz (using a 120kHz crystal), with
a voltage output swing of V+ to V-. The beeper output off state
is at the V+ rail. When crystals with different frequencies are
used, the frequency needed to drive the transducer can be
calculated by dividing the crystal frequency by 60.
Display
The ICL7149 uses a custom, duplexed drive display with
range, polarity, and low battery annunciators. With a 3V
peak display voltage, the RMS ON voltage will be 2.37V
minimum; RMS OFF voltage will be 1.06V maximum.
Because the display voltage is not adjustable, the display
should have a 10% ON threshold of about 1.4V. Most
display manufacturers supply a graph that shows contrast
versus RMS drive voltage. This graph can be used to
determine what the contrast ratio will be when driven by the
ICL7149. Most display thresholds decrease with increasing
temperature. The threshold at the maximum operating
temperature should be checked to ensure that the "off"
segments will not be turned "on" at high temperatures.
Crystal
The ICL7149 is designed to use a parallel resonant 120kHz
or 100kHz crystal with no additional external components.
The R
S
parameter should be less than 25k
to ensure
oscillation. Initial frequency tolerance of the crystal can be a
relatively loose 0.05%.
Switches
Because the logic input draws only about 5
A, switches
driving these inputs should be rated for low current, or "dry"
operations. The switches on the external inputs must be able
C
INT
Integrate Time
(
)
Integrate Current
(
)
Desired Integrator Swing
(
)
----------------------------------------------------------------------------------------------------
=
10,000 x 2 x Oscillator Period
(
) 0.4V/R
INTV
2V
(
)
-------------------------------------------------------------------------------------------------------------------------
=
ICL7149
10
to reliably switch low currents, and be able to handle
voltages in excess of 400V
AC
.
Reference Voltage Source
A voltage divider connected to V+ and Common is the
simplest source of reference voltage. While minimizing
external component count, this approach will provide the
same voltage tempco as the ICL7149 Common - about
100PPM/
o
C. To improve the tempco, an ICL8069 bandgap
reference may be used (see Figure 12). The reference
voltage source output impedance must be
R
DElNT
/4000.
Applications, Examples, and Hints
A complete autoranging 3
3
/
4
digit multimeter is shown in
Figure 13. The following sections discuss the functions of
specific components and various options.
Meter Protection
The ICL7149 and its external circuitry should be protected
against accidental application of 110/220V AC line voltages
on the
and current ranges. Without the necessary
precautions, the ICL7149 and its external components could
be damaged under such fault conditions. For the current
ranges, fast-blow fuses should be used between S5A in
Figure 13 and the 0.1
and 9.9 shunt resistors. For the
ranges, no additional protection circuitry is required.
However, the 10k
resistor connected to pin 14 must be
able to dissipate 1.2W or 4.8W for short periods of time
during accidental application of 110V or 220V
AC
line
voltages respectively.
DEINTEGRATE
INTEGRATE VOLT/
INTEGRATE CURRENT
REFERENCE INPUT
ANALOG COMMON
TRIPLE POINT
EXTERNAL
REFERENCE
10M
10K
1M
10M
10K
ICL8069
V+
FIGURE 12. EXTERNAL VOLTAGE REFERENCE CONNECTION
ICL7149
11
Printed Circuit Board Layout Considerations
Particular attention must be paid to rollover performance,
leakages, and guarding when designing the PCB for an
ICL7149-based multimeter.
Rollover Performance, Leakages, and Guarding
Because the ICL7149 system measures very low currents, it
is essential that the PCB have low leakage. Boards should
be properly cleaned after soldering. Areas of particular
importance are: 1) The INT V/
and INT l Pins; 2) The Triple
Point; 3) The R
DElNT
and the C
AZ
pins.
The conversion scheme used by the ICL7149 changes the
common mode voltage on the integrator and the capacitors
C
AZ
and C
lNT
during a positive deintegrate cycle. Stray
capacitance to ground is charged when this occurs,
removing some of the charge on C
lNT
and causing rollover
error. Rollover error increases about 1 count for each
picofarad of capacitance between C
AZ
or the Triple Point
and ground, and is seen as a zero offset for positive
voltages. Rollover error is not seen as gain error.
The rollover error causes the width of the +0 count to be
larger than normal. The ICL7149 will thus read zero until
several hundred microvolts are applied in the positive
direction. The ICL7149 will read -1 when approximately
-100
V is applied.
The rollover error can be minimized by guarding the Triple
Point and C
AZ
nodes with a trace connected to the C
lNT
pin,
(see Figure 14) which is driven by the output of the
integrator. Guarding these nodes with the output of the
integrator reduces the stray capacitance to ground, which
20
21
22
DEINT
INT V/
COMMON
LO
TRIPLE
10M
POINT
HI
INT I
/V/A
mA/
A
ICL7149
HOLD
HI
-DC/LO-AC
V
REF
V-
V+
BEEPER
DISPLAY
DRIVE
OUTPUTS
C
AZ
C
INT
OSC
OUT
OSC
IN
6, 8-9
31-44
BEEPER
INPUTS
V/
S4A
V
A
A
mA
S5A
16
19
14
15
18
17
26
25
COMMON
V+
V+
V-
A
A
V
mA
S4B
10k
1M
1M
9.9
10M
A
0.1
2W
28
S3
27
S3
V+
V+
13
12
10
24
1
F
ON/OFF
S1
9V
BATTERY
TANT
4.7
F
V+
ICL8069
PIN 17
LO BAT
AC
mAV
A
10k
120kHz
CRYSTAL
0.1
F
3.3nF
29
30
k
M
30K-
50K
+
+
+
-
10k
S2 CLOSED: HI
-DC
S3 CLOSED: HOLD READING
NOTES:
1. Crystal is a Statek or SaRonix CX-IV type.
2. Multimeter protection components have not been shown.
3. Display is from LXD, part number 38D8R02H (or Equivalent).
4. Beeper is from muRata, part number PKM24-4A0 (or Equivalent).
FIGURE 13. BASIC MULTIMETER APPLICATION CIRCUIT
21 22
20
19
18
17
16
FIGURE 14. PC BOARD LAYOUT
ICL7149
12
minimizes the charge error on C
lNT
and C
AZ
. If possible, the
guarding should be used on both sides of the PC board.
Stray Pickup
While the ICL7149 has excellent rejection of line frequency
noise and pickup in the DC ranges, any stray coupling will
affect the AC reading. Generally, the analog circuitry should
be as close as possible to the ICL7149. The analog circuitry
should be removed or shielded from any 120V AC power
inputs, and any AC sources such as LCD drive waveforms.
Keeping the analog circuit section close to the ICL7149 will
also help keep the area free of any loops, thus reducing
magnetically coupled interference coming from power
transformers, or other sources.
ICL7149
13
ICL7149
Metric Plastic Quad Flatpack Packages (MQFP)
D
D1
E E1
-A-
PIN 1
A2 A1
A
12
o
-16
o
12
o
-16
o
0
o
-7
o
0.40
0.016 MIN
L
0
o
MIN
PLANE
b
0.005/0.009
0.13/0.23
WITH PLATING
BASE METAL
SEATING
0.005/0.007
0.13/0.17
b1
-B-
e
0.008
0.20
A-B
S
D
S
C
M
0.076
0.003
-C-
-D-
-H-
Q44.10x10
(JEDEC MS-022AB ISSUE B)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.096
-
2.45
-
A1
0.004
0.010
0.10
0.25
-
A2
0.077
0.083
1.95
2.10
-
b
0.012
0.018
0.30
0.45
6
b1
0.012
0.016
0.30
0.40
-
D
0.515
0.524
13.08
13.32
3
D1
0.389
0.399
9.88
10.12
4, 5
E
0.516
0.523
13.10
13.30
3
E1
0.390
0.398
9.90
10.10
4, 5
L
0.029
0.040
0.73
1.03
-
N
44
44
7
e
0.032 BSC
0.80 BSC
-
Rev. 2 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane
.
4. Dimensions D1 and E1 to be determined at datum plane
.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. "N" is the number of terminal positions.
-C-
-H-
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