ChipFind - документация

Электронный компонент: ICL7104-16

Скачать:  PDF   ZIP

Document Outline

1
Features
16-Bit/14-Bit Binary Three-State Latched Outputs Plus
Polarity and Overrange
Ideally Suited for Interface to UARTs and
Microprocessors
Conversion on Demand or Continuously
Guaranteed Zero Reading for 0V Input
True Polarity at Zero Count for Precise Null Detection
Single Reference Voltage for True Ratiometric
Operation
Onboard Clock and Reference
Auto-Zero, Auto-Polarity
Accuracy Guaranteed to 1 Count
All Outputs TTL Compatible
4V Analog Input Range
Status Signal Available for External Sync, A/Z in
Preamp, Etc.
Description
The ICL7104, combined with the ICL8052 or ICL8068,
forms a member of Intersil' high performance A/D converter
family. The ICL7104-16, performs the analog switching and
digital function for a 16-bit binary A/D converter, with full
three-state output, UART handshake capability, and other
outputs for easy interfacing. The ICL7014-14 is a 14-bit
version. The analog section, as with all Intersil' integrating
converters, provides fully precise Auto-Zero, Auto-Polarity
(including
0 null indication), single reference operation,
very high input impedance, true input integration over a
constant period for maximum EMI rejection, fully
rationmetric operation, over-range indication, and a
medium quality built-in reference. The chip pair also offers
optional input buffer gain for high sensitivity applications, a
built-in clock oscillator, and output signals for providing an
external Auto-Zero capability in preconditioning circuitry,
synchronizing external multiplexers, etc.
Pinouts
ICL7104 (PDIP)
TOP VIEW
Part Number Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
ICL7104-14CPL
0 to 70
40 Ld PDIP
E40.6
lCL7104-16CPL
0 to 70
40 Ld PDIP
E40.6
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V++
DIG GND
STTS
POL
OR
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
NC
NC
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V-
COMP IN
REFCAP 1
V
REF
AZ
ANALOG
REFCAP 2
BUF IN
ANALOG I/P
V+
CE/LD
SEN
R/H
MODE
CLK 2
CLK 1
CLK 3
HBEN
LBEN
BIT 1
ICL7104-14
GND
V++
DIG GND
STTS
POL
OR
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
ICL7104-14
ICL7104-16
ICL7104-14
ICL7104-16
HBEN
MBEN
(OUTLINE DWGS DL,
JL, PL)
November 2000
ICL7104
14-Bit/16-Bit, Microprocessor-
Compatible, 2-Chip, A/D Converter
File Number
3091.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
NOT
RECO
MME
NDED
FOR
NEW
DES
IGNS
NO R
ECOM
MEN
DED
REPL
ACEM
ENT
conta
ct ou
r Tec
hnica
l Sup
port
Cent
er at
1-888
-INTE
RSIL
or w
ww.in
tersil
.com
/tsc
2
Functional Block Diagram
FIGURE 1. ICL8052A (8068A)/ICL7104 16-BIT/14-BIT A/D CONVERTER FUNCTIONAL DIAGRAM
A2
+
-
A3
+
-
INTEG.
COMP.
A1
+
-
BUFFER
14
11
9
INT OUT
-INT IN
BUF OUT
10
-BUF IN
-1.2V
2
50k
-15V
+5V
R
INT
C
INT
1
-15V
7
8
+15V
C
AZ
12
+INT IN
13
8052/8068
INT.
REF.
6
3
+BUF IN
5
REF
OUT
5k
10k
300pF
10
F
COMP
OUT
COMP IN 300k
39
36
33
8 9
6 7
12 13
10 11
16 17
14 15
20 21
18 19
5
4
14 13
16 15
10 9
12 11
6 5
8 7
2 1
4 3
OR POL
THREE-STATE OUTPUTS
LATCHES
COUNTER
24 HBEN
23 MBEN
22 LBEN
30 CE/LD
CONTROL LOGIC
ZERO
CROSSING
DETECTOR
29
27
28
7104
+BUF IN
AZ
SW3
SW5
SW4
SW6
SW8
SW2
SW9
SW7
SW1
34
REF CAP (2)
REF CAP (1)
38
C
REF
37
32
35
ANALOG
GND
ANALOG
INPUT
V
REF
SEN
MODE
R/H
BITS
3
STTS
26
CLOCK
25
CLOCK
40
-15V
2
1
+15V
31
+5V
(2)
(1)
Pin Descriptions
PIN NO.
SYMBOL
OPTION
DESCRIPTION
1
V++
Positive Supply Voltage: Nominally +15V.
2
GND
Digital Ground: 0V, ground return.
3
STTS
Status Output: HI during integrate and deintegrate until data is latched. LO when analog section
is in auto-zero configuration.
4
POL
Polarity: Three-state output. HI for positive input.
5
OR
Over Range: Three-state output.
6
BIT 16
BIT 14
-16
-14
Most Significant Bit (MSB).
7
BIT 15
BIT 13
-16
-14
DATA Bits: Three-state outputs. See Table 3 for format of ENABLES and bytes. HIGH = true.
8
BIT 14
BIT 12
-16
-14
9
BIT 13
BIT 11
-16
-14
10
BIT 12
BIT 10
-16
-14
11
BIT 11
BIT 9
-16
-14
12
BIT 10
NC
-16
-14
13
BIT 9
NC
-16
-14
14
BIT 8
15
BIT 7
16
BIT 6
17
BIT 5
18
BIT 4
19
BIT 3
20
BIT 2
ICL7104
3
21
BIT 1
Least Significant Bit (LSB).
22
LBEN
LOW BYTE ENABLE: If not in handshake mode (see pin 27) when LO (with CE/LD, pin 30)
activates low-order byte outputs, BITS 1-8. When in handshake mode (see pin 27), serves as a
low byte flag output. See Figures 11, 12, 13.
23
MBEN
-16
MID BYTE ENABLE: Activates Bits 9-16, see LBEN (pin 22)
HBEN
-14
HIGH BYTE ENABLE: Activates Bits 9-14, POL, OR, see LBEN (pin 22)
24
HBEN
-16
HIGH BYTE ENABLE: Activates POL, OR, see LBEN (pin 22).
CLOCK3
-14
RC oscillator pin: Can be used as clock output.
25
CLOCK 1
Clock Input: External clock or ocsillator.
26
CLOCK 2
Clock Output: Crystal or RC oscillator.
27
MODE
INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inputs directly
controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure
13). If HI, enables CE/LD, HBEN, MBEN and LBEN as outputs. Handshake mode will be entered
and data output as in Figures 11 and 12 at conversion completion.
28
R/H
RUN/HOLD: Input HI conversions continuously performed every 2
17
(-16) or 2
15
(-14) clock
pulses. Input LO conversion in progress completed, converter will stop in Auto-Zero 7 counts
before input integrate.
29
SEN
SEND ENABLE: Input controls timing of byte transmission in handshake mode. HI indicates
`send'.
30
CE/LD
CHIP ENABLE/ LOAD: WITH MODE (PIN 27) LO, CE/LD serves as a master output enable;
when HI, the bit outputs and POL, OR are disabled. With MODE HI, pin serves as a LOAD strobe
(-ve going) used in handshake mode. See Figures 11 and 12.
31
V+
Positive Logic Supply Voltage: Nominally +5V.
32
AN I/P
Analog Input: High Side.
33
BUF IN
Buffer Input: Buffer Analog to analog chip (ICL8052 or ICL8086).
34
REFCAP2
Reference Capacitor: Negative Side.
35
AN. GND
Analog Ground: Input low side and reference low side.
36
A-Z
Auto-Zero node.
37
V
REF
Voltage Reference: Input (positive side).
38
REFCAP1
Reference Capacitor: Positive side.
39
COMP-IN
Comparator Input: From 8052/8068.
40
V-
Negative Supply Voltage: Nominally -15V.
Pin Descriptions
(Continued)
PIN NO.
SYMBOL
OPTION
DESCRIPTION
ICL7104
4
Absolute Maximum Ratings
Thermal Information
V+ Supply (GND to V+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
V++ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32V
Positive Supply Voltage (GND to V++). . . . . . . . . . . . . . . . . . . . 17V
Negative Supply Voltage (GND to V-) . . . . . . . . . . . . . . . . . . . . -17V
Analog Input Voltage (Pins 32 - 39)(Note 4). . . . . . . . . . . . V++ to V-
Digital Input Voltage
(Pins 2 - 30) (Note 5) . . . . . . . . . . . . (GND - 0.3V) to (V+ + 0.3V)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
40 Ld PDIP Package . . . . . . . . . . . . . .
60
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
2. For supply voltages less than
15V, the absolute maximum input voltage is equal to the supply voltage.
3. Short circuit may be to ground or either supply. Rating applies to 70
o
C ambient temperature.
4. Input voltages may exceed the supply voltages provided the input current is limited to
100A.
5. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this
reason it is recommended that the power supply to the ICL7104 be established before any inputs from sources not on that supply are
applied.
ICL7104 Electrical Specifications
V+ = +5V, V++ = +15V, V- = -15V, T
A
= 25
o
C, f
CLOCK
= 200kHz
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
Clock Input, CLK 1
I
IN
V
IN
= +5V to 0V
2
7
30
A
Comparator I/P, COMP IN (Note 6)
I
IN
V
IN
= 0V to +5V
-10
0.001
10
A
Inputs with Pulldown, MODE
I
IH
V
IN
= +5V
1
5
30
A
I
IL
V
IN
= 0V
-10
0.01
10
A
Inputs with Pullups
SEN, R/H
LBEN, MBEN, HBEN, CE/LD (Note 7)
I
IH
V
IN
= +5V
-10
0.01
10
A
I
IL
V
IN
= 0V
-30
-5
-1
A
Input High Voltage, All Digital Inputs
V
IH
2.5
2.0
-
V
Input Low Voltage, All Digital Inputs
V
IL
-
1.5
1.0
V
Digital Outputs Three-Stated On,
LBEN, MBEN (16 Only), HBEN, CE/LD
BIT n, POL, OR (Note 8)
V
OL
I
OL
= 1.6mA
-
0.27
0.4
V
V
OH
I
OH
= -10
A
-
4.5
-
V
V
OH
I
OH
= -240
A
2.4
3.5
-
V
Digital Outputs Three-Stated Off
Bit n, POL, OR
I
OL
0
V
OUT
V+
-10
0.001
+10
A
Non Three-State Digital Output
STTS
V
OL
I
OL
= 3.2mA
-
0.3
0.4
V
V
OH
I
OH
= -400
A
2.4
3.3
-
V
Clock 2
V
OL
I
OL
= 320
A
-
0.5
-
V
V
OH
I
OH
= -320
A
-
4.5
-
V
Clock 3 (-14 Only)
V
OL
I
OL
= 1.6mA
-
0.27
0.4
V
V
OH
I
OH
= -320
A
2.4
3.5
-
V
Switch
Switch 1
r
DS(ON)
-
25k
-
Switches 2, 3
r
DS(ON)
-
4k
20k
Switches 4, 5, 6, 7, 8, 9
r
DS(ON)
-
2k
10k
Switch Leakage
I
D(OFF)
-
15
-
pA
Clock Frequency (Note 9)
f
CLOCK
DC
200
400
kHz
Supply Currents
+5V Supply Current
All outputs high impedance
I+
Frequency = 200kHz
-
200
600
A
+5V Supply Current
I++
Frequency = 200kHz
-
0.3
1.0
mA
-5V Supply Current
I-
Frequency = 200kHz
-
25
200
A
ICL7104
5
Supply Voltage Range
Logic Supply
V+
Note 10
4
-
11
V
Positive Supply
V++
10
-
16
V
Negative Supply
V-
-16
-
-10
V
NOTES:
6. This specification applies when not in Auto-Zero phase.
7. Apply only when these pins are inputs, i.e., the mode pin is low, and the 7104 is not in handshake mode.
8. Apply only when these pins are outputs, i.e., the mode pin is high, or the 7104 is in handshake mode.
9. Clock circuit shown in Figures 14 and 15.
10. V+ must not be more positive than V++.
System Electrical Specifications: ICL8068/ICL7104
V++ = +15V, V+ = +5V, V- = -15V, f
CLOCK
= 200kHz (Note 16)
PARAMETER
TEST
CONDITIONS
ICL8068A/ICL7104-14
ICL8068A/ICL7104-16
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Zero Input Reading
V
IN
= 0V, V
REF
= 2V
-00000
00000 +00000
-00000
00000 +00000
Counts
Ratiometric Error (Note 13)
V
IN
= V
REF
= 2V
-1
0
1
-1
0
1
LSB
Linearity Over
Full Scale (Error of
Reading from Best Straight Line)
-4V
V
IN
+4V
-
0.5
1
-
0.5
1
LSB
Differential Linearity (Difference
between Worst Case Step of Adjacent
Counts and Ideal Step)
-4V
V
IN
+4V
-
0.01
-
-
0.01
-
LSB
Rollover Error (Difference in Reading
for Equal Positive & Negative Voltage
Near Full Scale)
-V
IN
= +V
IN
4V
-
0.5
1
-
0.5
1
LSB
Noise (P-P Value Not Exceeded 95% of
Time)
V
IN
= 0V,
Full Scale = 4V
-
2
-
-
2
-
V
Leakage Current at Input (Note 14)
V
IN
= 0V
-
100
165
-
100
165
pA
Zero Reading Drift
V
IN
= 0V,
0
o
C to 70
o
C
-
0.5
-
-
0.5
-
V/
o
C
Scale Factor Temperature Coefficient
(Note 15)
V
IN
= 4V,
0
o
C to 50
o
C
ext. ref. 0ppm/
o
C
-
2
5
-
2
5
ppm/
o
C
System Electrical Specifications: ICL8052/ICL7104
V++ = +15V, V+ = +5V, V- = -15V, f
CLOCK
= 200kHz
(Note 16)
PARAMETER
TEST
CONDITIONS
ICL8052A/ICL7104-14
ICL8052A/ICL7104-16
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Zero Input Reading
V
IN
= 0V, V
REF
= 2V
-00000
00000 +00000
-00000
00000 +00000
Counts
Ratiometric Error (Note 15)
V
IN
= V
REF
= 2V
-1
0
1
-1
0
1
LSB
Linearity Over
Full Scale (Error of
Reading from Best Straight Line)
-4V
V
IN
+4V
-
0.5
1
-
0.5
1
LSB
Differential Linearity (Difference
between Worst Case Step of Adjacent
Counts and Ideal Step)
-4V
V
IN
+4V
-
0.01
-
-
0.01
-
LSB
Rollover Error (Difference in Reading
for Equal Positive and Negative Voltage
Near Full Scale)
-V
IN
= +V
IN
4V
-
0.5
1
-
0.5
1
LSB
Noise (Peak-to-Peak Value Not
Exceeded 95% of Time)
V
IN
= 0V,
Full Scale = 4V
-
30
-
-
30
-
V
ICL7104 Electrical Specifications
V+ = +5V, V++ = +15V, V- = -15V, T
A
= 25
o
C, f
CLOCK
= 200kHz (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
ICL7104