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changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

May 1994

INTEL CORPORATION 1995

Order Number 271305-001

VE28F008

8 MBIT (1 MBIT x 8) FLASH MEMORY

High-Density Symmetrically Blocked
Architecture

Sixteen 64 Kbyte Blocks

Avionics Temperature Range

40 C to

125 C

Extended Cycling Capability

10K Block Erase Cycles
160K Block Erase
Cycles per Chip

Automated Byte Write and Block Erase

Command User Interface
Status Register

System Performance Enhancements

RY BY Status Output
Erase Suspend Capability

Very High-Performance Read

95 ns Maximum Access Time

SRAM-Compatible Write Interface

Hardware Data Protection Feature

Erase Write Lockout during Power
Transitions

Industry Standard Packaging

40-Lead TSOP

ETOX

III Nonvolatile Flash

Technology

12V Byte Write Block Erase

Independent Software Vendor Support

Microsoft Flash File System (FFS)

Intel's VE28F008 8-Mbit Flash File

Memory revolutionizes the design of high performance and durable

mass storage memory systems for the Industrial Avionics and Military markets With its innovative features
like low power blocked architecture high read write performance and expanded temperature range any
design or mission is free from the dependence on battery backed up memory or highly sensitive and slow
rotating media drives

Using the VE28F008 in a PCMCIA 2 1 Flash Memory card ATA drive or any size or shape module will allow
data application or operating systems to be updated or collected anywhere and at anytime This data on
demand feature ensures protection from obsolesce through field or in system software updates

The VE28F008's highly integrated Command User Interface and Write State Machine decreases the size and
complexity of system software while providing high read write and erase performance The sixteen separately
erasable 64 Kbyte blocks along with a multiple write data protection system provides assurance that highly
important data will be available when needed

The VE28F008 is offered in a 40-lead TSOP (Thin Small Outline Package) which is capable of performing in
temperatures from b40 C to a125 C It employs advanced CMOS circuitry for systems requiring low power
consumption and noise immunity The VE28F008's 95 ns access time provides superior performance when
compared to magnetic mass storage

Manufactured on Intel's 0 8 micron ETOX

III process the VE28F008 provides the highest levels of quality

reliability and cost effectiveness

Microsoft is a trademark of Microsoft Corporation

VE28F008

PRODUCT OVERVIEW

The VE28F008 is a high-performance 8 Mbit
(8 388 608 bit) memory organized as 1 Mbyte
(1 048 576 bytes) of 8 bits each Sixteen 64 Kbyte
(65 536 byte) blocks are included on the VE28F008
A memory map is shown in Figure 4 of this specifica-
tion A block erase operation erases one of the six-
teen blocks of memory in typically 1 6 seconds in-
dependent of the remaining blocks Each block can
be independently erased and written 10 000 cycles
Erase Suspend

mode allows system software to

suspend block erase to read data or execute code
from any other block of the VE28F008

The VE28F008 is available in a 40-lead TSOP pack-
age Pinout is shown in Figure 2 of this specification

The Command User Interface serves as the inter-
face between the microprocessor or microcontroller
and the internal operation of the VE28F008

Byte Write and Block Erase Automation

allow

byte write and block erase operations to be execut-
ed using a two-write command sequence to the
Command User Interface The internal Write State
Machine

(WSM) automatically executes the algo-

rithms and timings necessary for byte write and
block

erase

operations

including

verifications

thereby unburdening the microprocessor or micro-
controller Writing of memory data is performed in
byte increments typically within 9 ms an 80% im-
provement over current flash memory products I

byte write and block erase currents

are 30 mA

maximum V

byte write and block erase volt-

age

is 11 4V to 12 6V

The Status Register indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation

The RY BY output gives an additional indicator of
WSM activity providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase
for example) Status polling using RY BY minimizes
both CPU overhead and system power consump-
tion When low RY BY indicates that the WSM is
performing a block erase or byte write operation
RY BY high indicates that the WSM is ready for new
commands block erase is suspended or the device
is in deep powerdown mode

Maximum access time is 95 ns (t

ACC

)

over the avi-

onics temperature range (b40 C to a125 C) and
over V

supply voltage range 4 75V to 5 25V I

active current

(CMOS Read) is 35 mA maximum

at 8 MHz

When the CE and RP pins are at V

the I

CMOS

Standby

mode is enabled

A Deep Powerdown mode is enabled when the RP
pin is at GND minimizing power consumption and
providing write protection Reset time of 400 ns is
required from RP switching high until outputs are val-
id to read attempts Equivalently the device has a
wake time of 1 ms from RP high until writes to the
Command User Interface are recognized by the
VE28F008 With RP at GND the WSM is reset and
the Status Register is cleared

VE28F008

271305 � 1

Figure 1 Block Diagram

Table 1 Pin Description

Symbol

Type

Name and Function

� A

INPUT

ADDRESS INPUTS

for memory addresses Addresses are internally

latched during a write cycle

� DQ

INPUT OUTPUT

DATA INPUT OUTPUTS

Inputs data and commands during Command

User Interface write cycles outputs data during memory array Status
Register and Identifier read cycles The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled Data is internally latched during a write cycle

INPUT

CHIP ENABLE

Activates the device's control logic input buffers

decoders and sense amplifiers CE is active low CE high deselects the
memory device and reduces power consumption to standby levels

INPUT

RESET DEEP POWERDOWN

Puts the device in the deep powerdown

mode RP is active low RP high gates normal operation RP also locks
out block erase or byte write operations when active low providing data
protection during power transitions RP active resets internal
automation Exit from Deep Powerdown sets device to read-array mode

INPUT

OUTPUT ENABLE

Gates the device's outputs through the data buffers

during a read cycle OE is active low

INPUT

WRITE ENABLE

Controls writes to the Command User Interface and

array blocks WE is active low Addresses and data are latched on the
rising edge of the WE pulse

VE28F008

271305 � 3

Figure 3 VE28F008 Array Interface to Intel386

SL Microprocessor Superset through PI Bus

(Including RY BY Masking and Selective Powerdown) for DRAM Backup during System SUSPEND

Resident O S and Applications and Motherboard Solid-State Disk

PRINCIPLES OF OPERATION

The VE28F008 includes on-chip write automation to
manage write and erase functions The Write State
Machine allows for 100% TTL-level control inputs
fixed power supplies during block erasure and byte
write and minimal processor overhead with RAM-
like interface timings

After initial device powerup or after return from
deep powerdown mode (see Bus Operations) the
VE28F008 functions as a read-only memory Manip-
ulation of external memory-control pins allow array
read standby and output disable operations Both
Status

and

intelligent

identifier

can

also be accessed through the Command User Inter-
face when V

PPL

This same subset of operations is also available
when high voltage is applied to the V

pin In addi-

tion high voltage on V

enables successful block

erasure and byte writing of the device All functions
associated with altering memory contents

byte

write block erase status and intelligent identifier
are accessed via the Command User Interface and
verified thru the Status Register

Commands are written using standard microproces-
sor write timings Command User Interface contents
serve as input to the WSM which controls the block

VE28F008

erase and byte write circuitry Write cycles also inter-
nally latch addresses and data needed for byte write
or block erase operations With the appropriate com-
mand written to the register standard microproces-
sor read timings output array data access the intelli-
gent identifier codes or output byte write and block
erase status for verification

Interface software to initiate and poll progress of in-
ternal byte write and block erase can be stored in
any of the VE28F008 blocks This code is copied to
and executed from system RAM during actual flash
memory update After successful completion of byte
write and or block erase code data reads from the
VE28F008 are again possible via the Read Array
command Erase suspend resume capability allows
system software to suspend block erase to read
data and execute code from any other block

FFFFF

64 Kbyte Block

EFFFF

F0000

64 Kbyte Block

DFFFF

E0000

64 Kbyte Block

CFFFF

D0000

64 Kbyte Block

BFFFF

C0000

64 Kbyte Block

AFFFF

B0000

64 Kbyte Block

9FFFF

A0000

64 Kbyte Block

8FFFF

90000

64 Kbyte Block

7FFFF

80000

64 Kbyte Block

6FFFF

70000

64 Kbyte Block

5FFFF

60000

64 Kbyte Block

4FFFF

50000

64 Kbyte Block

3FFFF

40000

64 Kbyte Block

2FFFF

30000

64 Kbyte Block

1FFFF

20000

64 Kbyte Block

0FFFF

10000

64 Kbyte Block

00000

Figure 4 Memory Map

Command User Interface and Write
Automation

An on-chip state machine controls block erase and
byte write freeing the system processor for other
tasks After receiving the Erase Setup and Erase
Confirm commands

the state machine controls

block pre-conditioning and erase returning progress
via the Status Register and RY BY output Byte
write is similarly controlled after destination address
and expected data are supplied The program and
erase algorithms of past Intel Flash memories are
now regulated by the state machine including pulse
repetition where required and internal verification
and margining of data

Data Protection

Depending on the application the system designer
may choose to make the V

power supply switcha-

ble (available only when memory byte writes block
erases are required) or hardwired to V

PPH

When

PPL

memory contents cannot be altered

The VE28F008 Command User Interface architec-
ture provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V

Additionally all functions are dis-

abled whenever V

is below the write lockout volt-

age V

LKO

or when RP is at V

The VE28F008 ac-

commodates either design practice and encourages
optimization of the processor-memory interface

The two-step byte write block erase Command User
Interface write sequence provides additional soft-
ware write protection

BUS OPERATION

Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles

Read

The VE28F008 has three read modes The memory
can be read from any of its blocks and information
can be read from the intelligent identifier or Status
Register V

can be at either V

PPL

or V

PPH

The first task is to write the appropriate read mode
command to the Command User Interface (array in-
telligent

identifier

Status

The

VE28F008 automatically resets to Read Array mode
upon initial device powerup or after exit from deep
powerdown The VE28F008 has four control pins
two of which must be logically active to obtain

VE28F008

Table 2 Bus Operations

Mode

Notes

0�7

RY BY

Read

1 2 3

OUT

Output Disable

High Z

Standby

High Z

PowerDown

High Z

Intelligent Identifier (Mfr)

89H

Intelligent Identifier (Device)

A2H

Write

3 4 5

NOTES
1 Refer to DC Characteristics When V

PPL

memory contents can be read but not written or erased

2 X can be V

or V

for control pins and addresses and V

PPL

or V

PPH

for V

See DC Characteristics for V

PPL

and V

PPH

voltages
3 RY BY is V

when the Write State Machine is executing internal block erase or byte write algorithms It is V

when the

WSM is not busy in Erase Suspend mode or deep powerdown mode
4 Command writes involving block erase or byte write are only successfully executed when V

PPH

5 Refer to Table 3 for valid D

during a write operation

data at the outputs Chip Enable (CE) is the device
selection control and when active enables the se-
lected memory device Output Enable (OE) is the
data input output (DQ

� DQ

) direction control and

when active drives data from the selected memory
onto the I O bus RP and WE must also be at V

Figure 8 illustrates read bus cycle waveforms

Output Disable

With OE at a logic-high level (V

) the device out-

puts are disabled

Output pins (DQ

� DQ

) are

placed in a high-impedance state

Standby

CE at a logic-high level (V

) places the VE28F008

in standby mode Standby operation disables much
of the VE28F008's circuitry and substantially reduc-
es device power consumption The outputs (DQ

�

) are placed in a high-impedence state indepen-

dent of the status of OE If the VE28F008 is dese-
lected during block erase or byte write the device
will continue functioning and consuming normal ac-
tive power until the operation completes

Deep Power-Down

The VE28F008 offers a deep powerdown feature
entered when RP is at V

During read modes RP at

a logic-low level (V

) deselects the memory places

output drivers in a high-impedence state and turns

off all internal circuits The VE28F008 requires time
t

PHQV

(see AC Characteristics-Read-Only Opera-

tions) after return from powerdown until initial mem-
ory access outputs are valid After this wakeup inter-
val normal operation is restored The Command
User Interface is reset to Read Array mode and the
upper 5 bits of the Status Register are cleared to
value 10000 upon return to normal operation

During block erase or byte write modes RP at a log-
ic-low level (V

) will abort either operation Memory

contents of the block being altered are no longer
valid as the data will be partially written or erased
Time t

PHWL

after RP goes to logic-high (V

) is re-

quired before another command can be written

Intelligent Identifier Operation

The intelligent identifier operation outputs the manu-
facturer code 89H and the device code A2H for
the VE28F008 The system CPU can then automati-
cally match the device with its proper block erase
and byte write algorithms

The manufacturer and device codes are read via the
Command User Interface Following a write of 90H
to the Command User Interface a read from ad-
dress location 00000H outputs the manufacturer
code (89H) A read from address location 00001H
outputs the device code (A2H) It is not necessary to
have high voltage applied to V

to read the intelli-

gent identifier from the Command User Interface

VE28F008

Table 3 Command Definitions

Command

Cycles

Req'd

Bus

Notes

First Bus Cycle

Second Bus Cycle

Operation Address Data Operation Address Data

Read Array Reset

Write

FFH

Intelligent Identifier

2 3 4

Write

90H

Read

IID

Read Status Register

Write

70H

Read

SRD

Clear Status Register

Write

50H

Erase Setup Erase Confirm

Write

20H

Write

D0H

Erase Suspend Erase Resume

Write

B0H

Write

D0H

Byte Write Setup Write

2 3 5

Write

40H

Write

Alternate Byte Write Setup Write

2 3 5

Write

10H

Write

NOTES
1 Bus operations are defined in Table 2
2 IA

Identifier Address 00H for manufacturer code 01H for device code

Address within the block being erased

Address of memory location to be written

3 SRD

Data read from Status Register See Table 4 for a description of the Status Register bits

Data to be written at location WA Data is latched on the rising edge of WE

IID

Data read from intelligent identifiers

4 Following the intelligent identifier command two read operations access manufacture and device codes
5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command
6 Commands other than those shown above are reserved by Intel for future device implementations and should not be
used

Write

Writes to the Command User Interface enable read-
ing of device data and intelligent identifier They also
control inspection and clearing of the Status Regis-
ter Additionally when V

PPH

the Command

User Interface controls block erasure and byte write
The contents of the interface register serve as input
to the internal write state machine

The Command User Interface itself does not occupy
an addressable memory location The interface reg-
ister is a latch used to store the command and ad-
dress and data information needed to execute the
command Erase Setup and Erase Confirm com-
mands require both appropriate command data and
an address within the block to be erased The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written while the Byte Write command consists of
the data to be written and the address of the loca-
tion to be written

The Command User Interface is written by bringing
WE to a logic-low level (V

) while CE is low Ad-

dresses and data are latched on the rising edge of
WE

Standard microprocessor write timings are

used

Refer to AC Write Characteristics and the AC Wave-
forms for Write Operations Figure 9 for specific tim-
ing parameters

COMMAND DEFINITIONS

When V

PPL

is applied to the V

pin read opera-

tions from the Status Register intelligent identifier
or array blocks are enabled Placing V

PPH

on V

enables successful byte write and block erase oper-
ations as well

Device operations are selected by writing specific
commands into the Command User Interface Table
3 defines the VE28F008 commands

Read Array Command

Upon initial device powerup and after exit from deep
powerdown mode the VE28F008 defaults to Read
Array mode This operation is also initiated by writing
FFH into the Command User Interface Microproces-
sor read cycles retrieve array data The device re-
mains enabled for reads until the Command User
Interface contents are altered Once the internal
Write State Machine has started a block erase or
byte write operation the device will not recognize

VE28F008

Table 4 Status Register Definitions

WSMS

ESS

BWS

VPPS

SR 7

WRITE STATE MACHINE STATUS

Ready

Busy

SR 6

ERASE SUSPEND STATUS

Erase Suspended

Erase in Progress Completed

SR 5

ERASE STATUS

Error in Block Erasure

Successful Block Erase

SR 4

BYTE WRITE STATUS

Error in Byte Write

Successful Byte Write

SR 3

STATUS

Low Detect Operation Abort

SR 2�SR 0

RESERVED FOR FUTURE
ENHANCEMENTS

These bits are reserved for future use and
should be masked out when polling the Status
Register

NOTES

RY BY or the Write State Machine Status bit must first
be checked to determine byte write or block erase com-
pletion before the Byte Write or Erase Status bit are
checked for success

If the Byte Write AND Erase Status bits are set to ``1''s
during a block erase attempt an improper command se-
quence was entered Attempt the operation again

If V

low status is detected the Status Register must be

cleared before another byte write or block erase opera-
tion is attempted

The V

Status bit unlike an A D converter does not

provide continuous indication of V

level The WSM in-

terrogates the V

level only after the byte write or block

erase command sequences have been entered and in-
forms the system if V

has not been switched on The

Status bit is not guaranteed to report accurate feed-

back between V

PPL

and V

PPH

the Read Array command until the WSM has com-
pleted its operation The Read Array command is
functional when V

PPL

or V

PPH

Intelligent Identifier Command

The VE28F008 contains an intelligent identifier oper-
ation initiated by writing 90H into the Command
User Interface Following the command write a read
cycle from address 00000H retrieves the manufac-
turer code of 89H A read cycle from address 01H
returns the device code of A2H To terminate the
operation it is necessary to write another valid com-
mand into the register Like the Read Array com-
mand the intelligent identifier command is functional
when V

PPL

or V

PPH

Read Status Register Command

The VE28F008 contains a Status Register which
may be read to determine when a byte write or block
erase operation is complete and whether that oper-
ation completed successfully The Status Register
may be read at any time by writing the Read Status
Register command (70H) to the Command User In-
terface After writing this command all subsequent
read operations output data from the Status Regis-
ter until another valid command is written to the

Command User Interface

The contents of the

Status Register are latched on the falling edge of OE
or CE whichever occurs last in the read cycle OE or
CE must be toggled to V

before further reads to

update the Status Register latch The Read Status
Register command functions when V

PPL

PPH

Clear Status Register Command

The Erase Status and Byte Write Status bits are set
to ``1''s by the Write State Machine and can only be
reset by the Clear Status Register Command These
bits indicate various failure conditions (see Table 4)
By allowing system software to control the resetting
of these bits several operations may be performed
(such as cumulatively writing several bytes or eras-
ing multiple blocks in sequence) The Status Regis-
ter may then be polled to determine if an error oc-
curred during that sequence This adds flexibility to
the way the device may be used

Additionally the V

Status bit (SR 3) MUST be re-

set by system software before further byte writes or
block erases are attempted To clear the Status
Register the Clear Status Register command (50H)
is written to the Command User Interface The Clear
Status Register command is functional when V

PPL

or V

PPH

VE28F008

Erase Setup Erase Confirm
Commands

Erase is executed one block at a time initiated by a
two-cycle command sequence

An Erase Setup

command (20H) is first written to the Command User
Interface followed by the Erase Confirm command
(D0H) These commands require both appropriate
sequencing and an address within the block to be
erased to FFH Block preconditioning erase and
verify are all handled internally by the Write State
Machine invisible to the system After the two-com-
mand erase sequence is written to it the VE28F008
automatically outputs Status Register data when
read (see Figure 6 Block Erase Flowchart) The
CPU can detect the completion of the erase event
by analyzing the output of the RY BY pin or the
WSM Status bit of the Status Register

When erase is completed the Erase Status bit
should be checked If erase error is detected the
Status Register should be cleared The Command
User Interface remains in Read Status Register
mode until further commands are issued to it

This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased Also reliable block erasure can only
occur when V

PPH

In the absence of this high

voltage memory contents are protected against era-
sure If block erase is attempted while V

PPL

the V

Status bit will be set to ``1'' Erase attempts

while V

PPL

PPH

produce spurious results

and should not be attempted

Erase Suspend Erase Resume
Commands

The Erase Suspend command allows block erase
interruption in order to read data from another block
of memory Once the erase process starts writing
the Erase Suspend command (B0H) to the Com-
mand User Interface requests that the WSM sus-
pend the erase sequence at a predetermined point
in the erase algorithm The VE28F008 continues to
output Status Register data when read after the
Erase Suspend command is written to it Polling the
WSM status and Erase Suspend status bits will de-
termine when the erase operation has been sus-
pended (both will be set to ``1'') RY BY will also
transition to V

At this point a Read Array command can be written
to the Command User Interface to read data from
blocks other than that which is suspended The only
other valid commands at this time are Read Status
Register (70H) and Erase Resume (D0H) at which
time the WSM will continue with the erase process
The Erase Suspend status and WSM status bits of
the Status Register will be automatically cleared and
RY BY will return to V

After the Erase Resume

command is written to it the VE28F008 automatical-
ly outputs Status Register data when read (see Fig-
ure 7

Erase Suspend Resume Flowchart)

must remain at V

PPH

while the VE28F008 is in Erase

Suspend

Byte Write Setup Write Commands

Byte write is executed by a two-command sequence
The Byte Write Setup command (40H) is written to
the Command User Interface followed by a second
write specifying the address and data (latched on
the rising edge of WE) to be written The WSM then
takes over controlling the byte write and write verify
algorithms internally After the two-command byte
write sequence is written to it the VE28F008 auto-
matically outputs Status Register data when read
(see Figure 5 Byte Write Flowchart) The CPU can
detect the completion of the byte write event by ana-
lyzing the output of the RY BY pin or the WSM
status bit of the Status Register Only the Read
Status Register command is valid while byte write is
active

When byte write is complete the Byte Write status
bit should be checked If byte write error is detected
the Status Register should be cleared The internal
WSM verify only detects errors for ``1''s that do not
successfully write to ``0''s The Command User In-
terface remains in Read Status Register mode until
further commands are issued to it If byte write is
attempted while V

PPL

the V

Status bit will

be set to ``1'' Byte write attempts while

PPL

PPH

produce spurious results and should not be attempt-
ed

VE28F008

EXTENDED BLOCK ERASE BYTE
WRITE CYCLING

Intel has designed extended cycling capability into
its

ETOX

flash

memory

technologies

The

VE28F008 is designed for 10 000 byte write block
erase cycles on each of the sixteen 64 Kbyte blocks
Low electric fields advanced oxides and minimal ox-
ide area per cell subjected to the tunneling electric
field combine to greatly reduce oxide stress and the
probability of failure A 20 Mbyte solid-state drive us-
ing an array of VE28F008s has a MTBF (Mean Time
Between Failure) of 3 33 million hours

(1)

AUTOMATED BYTE WRITE

The VE28F008 integrates the Quick-Pulse program-
ming algorithm of prior Intel Flash devices on-chip
using the Command User Interface Status Register
and Write State Machine (WSM) On-chip integration
dramatically simplifies system software and provides
processor interface timings to the Command User
Interface and Status Register WSM operation inter-
nal verify and V

high voltage presence are moni-

tored and reported via the RY BY output and appro-
priate Status Register bits Figure 5 shows a system
software flowchart for device byte write The entire
sequence is performed with V

at V

PPH

Byte write

abort occurs when RP transitions to V

or V

drops to V

PPL

Although the WSM is halted byte

data is partially written at the location where byte
write was aborted Block erasure or a repeat of byte
write is required to initialize this data to a known
value

AUTOMATED BLOCK ERASE

As above the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally includ-
ing all preconditioning of block data WSM opera-
tion erase success and V

high voltage presence

are monitored and reported through RY BY and the
Status Register Additionally if a command other
than Erase Confirm is written to the device following
Erase Setup both the Erase Status and Byte Write
Status bits will be set to ``1''s When issuing the
Erase Setup and Erase Confirm commands they
should be written to an address within the address
range of the block to be erased Figure 6 shows a
system software flowchart for block erase

Erase typically takes 1 6 seconds per block The
Erase Suspend Erase Resume command sequence
allows suspension of this erase operation to read
data from a block other than that in which erase is
being performed A system software flowchart is
shown in Figure 7

The entire sequence is performed with V

at V

PPH

Abort occurs when RP transitions to V

or V

falls

to V

PPL

while erase is in progress Block data is

partially erased by this operation and a repeat of
erase is required to obtain a fully erased block

DESIGN CONSIDERATIONS

Three-Line Output Control

The VE28F008 will often be used in large memory
arrays Intel provides three control inputs to accom-
modate multiple memory connections Three-line
control provides for

a) lowest possible memory power dissipation

b) complete assurance that data bus contention will

not occur

To efficiently use these control inputs an address
decoder should enable CE while OE should be con-
nected to all memory devices and the system's
READ control line This assures that only selected
memory devices have active outputs while deselect-
ed memory devices are in Standby Mode Finally
RP should either be tied to the system RESET or
connected to V

if unused

RY BY and Byte Write Block Erase
Polling

RY BY is a full CMOS output that provides a hard-
ware method of detecting byte write and block erase
completion It transitions low time t

WHRL

after a

write or erase command sequence is written to the
VE28F008 and returns to V

when the WSM has

finished executing the internal algorithm

RY BY can be connected to the interrupt input of
the system CPU or controller It is active at all times
not tri-stated if the VE28F008 CE or OE inputs are
brought to V

RY BY is also V

when the device

is in Erase Suspend or deep powerdown modes

(1)

Assumptions 10 Kbyte file written every 10 minutes (20 Mbyte array) (10 Kbyte file) e 2 000 file writes before erase required

(2000 files writes erase)

(10 000 cycles per VE28F008 block) e 20 million file writes

(20

file writes)

(10 min write)

(1 hr 60 min) e 3 33

MTBF

VE28F008

271305 � 4

Bus

Command

Comments

Operation

Write

Byte Write

Data

40H (10H)

Setup

Address

Byte to be written

Write

Byte Write

Data to be written
Address

Byte to be written

Standby Read

Check RY BY
V

Ready V

Busy

Read Status Register
Check SR 7
1

Ready 0

Busy

Toggle OE or CE to update
Status Register

Repeat for subsequent bytes

Full status check can be done after each byte or after a
sequence of bytes

Write FFH after the last byte write operation to reset the
device to Ready Array Mode

FULL STATUS CHECK PROCEDURE

271305 � 5

Bus

Command

Comments

Operation

Optional

CPU may already have read
Status Register data in WSM

Read

Ready polling above

Standby

Check SR 3
1

Low Detect

Standby

Check SR 4
1

Byte Write Error

SR 3 MUST be cleared if set during a byte write attempt
before further attempts are allowed by the Write State
Machine

SR 4 is only cleared by the Clear Status Register Command
in cases where multiple bytes are written before full status is
checked

If error is detected clear the Status Register before
attempting retry or other error recovery

Figure 5 Automated Byte Write Flowchart

VE28F008

271305 � 6

Bus

Command

Comments

Operation

Write

Erase

Data

20H

Setup

Address

Within block to be

erased

Write

Erase

Data

D0H

Address

Within block to be

erased

Standby Read

Check RY BY
V

Ready V

Busy

Read Status Register
Check SR 7
1

Ready 0

Busy

Toggle OE or CE to update
Status Register

Repeat for subsequent bytes

Full status check can be done after each block or after a
sequence of blocks

Write FFH after the last block erase operation to reset the
device to Ready Array Mode

FULL STATUS CHECK PROCEDURE

271305 � 7

Bus

Command

Comments

Operation

Optional

CPU may already have read
Status Register data in WSM

Read

Ready polling above

Standby

Check SR 3
1

Low Detect

Standby

Check SR 4 5
Both 1

Command Sequence

Error

Standby

Check SR 5
1

Block Erase Error

SR 3 MUST be cleared if set during a block erase attempt
before further attempts are allowed by the Write State
Machine

SR 5 is only cleared by the Clear Status Register Command
in cases where multiple blocks are erased before full status is
checked

If error is detected clear the Status Register before
attempting retry or other error recovery

Figure 6 Automated Block Erase Flowchart

VE28F008

Power Supply Decoupling

Flash memory power switching characteristics re-
quire careful device decoupling System designers
are interested in 3 supply current issues standby
current levels (I

) active current levels (I

) and

transient peaks produced by falling and rising edges
of CE Transient current magnitudes depend on the
device outputs' capacitive and inductive loading
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks
Each device should have a 0 1 mF ceramic capacitor
connected between each V

and GND and be-

tween its V

and GND These high frequency low

inherent-inductance capacitors should be placed as
close as possible to package leads Additionally for
every 8 devices a 4 7 mF electrolytic capacitor
should be placed at the array's power supply con-
nection between V

and GND The bulk capacitor

will overcome voltage slumps caused by PC board
trace inductances

Trace on Printed Circuit Boards

Writing flash memories while they reside in the tar-
get system requires that the printed circuit board
designer pay attention to the V

power supply

trace The V

pin supplies the memory cell current

for writing and erasing Use similar trace widths and
layout considerations given to the V

power bus

Adequate V

supply traces and decoupling will de-

crease V

voltage spikes and overshoots

RP Transitions and the

Command Status Registers

Byte write and block erase completion are not guar-
anteed if V

drops below V

PPH

If the V

Status bit

of the Status Register (SR 3) is set to ``1'' a Clear
Status Register command MUST be issued before
further byte write block erase attempts are allowed
by the WSM Otherwise the Byte Write (SR 4) or
Erase (SR 5) Status bits of the Status Register will
be set to ``1''s if error is detected RP transitions to
V

during byte write and block erase also abort the

operations Data is partially altered in either case
and the command sequence must be repeated after
normal operation is restored Device poweroff or RP
transitions to V

clear the Status Register to initial

value 10000 for the upper 5 bits

The Command User Interface latches commands as
issued by system software and is not altered by V

or CE transitions or WSM actions Its state upon
powerup after exit from deep powerdown or after
V

transitions below V

LKO

is Read Array Mode

After byte write or block erase is complete even
after V

transitions down to V

PPL

the Command

User Interface must be reset to Read Array mode via
the Read Array command if access to the memory
array is desired

Power Up Down Protection

The VE28F008 is designed to offer protection
against accidental block erasure or byte writing dur-
ing

power

transitions

Upon

power-up

the

VE28F008 is indifferent as to which power supply
V

or V

powers up first Power supply sequenc-

ing is not required Internal circuitry in the VE28F008
ensures that the Command User Interface is reset to
the Read Array mode on power up

A system designer must guard against spurious
writes for V

voltages above V

LKO

when V

active Since both WE and CE must be low for a
command write driving either to V

will inhibit

writes The Command User Interface architecture
provides an added level of protection since altera-
tion of memory contents only occurs after success-
ful completion of the two-step command sequences

Finally the device is disabled until RP is brought to
V

regardless of the state of its control inputs This

provides an additional level of memory protection

Power Dissipation

When designing portable systems designers must
consider battery power consumption not only during
device operation but also for data retention during
system idle time Flash nonvolatility increases us-
able battery life because the VE28F008 does not
consume any power to retain code or data when the
system is off

In addition the VE28F008's deep powerdown mode
ensures extremely low power dissipation even when
system power is applied For example portable PCs
and other power sensitive applications using an ar-
ray of VE28F008s for solid-state storage can lower
RP to V

in standby or sleep modes reducing pow-

er consumption If access to the VE28F008 is again
needed the part can again be read following the
t

PHQV

and t

PHWL

wakeup cycles required after RP is

first raised back to V

See AC Characteristics

Read-Only and Write Operations and Figures 10 and
11 for more information

VE28F008

ABSOLUTE MAXIMUM RATINGS

Operating Temperature

40 C to a125 C

Temperature Under Bias

40 C to a125 C

Storage Temperature

65 C to a125 C

Voltage on Any Pin

(except V

and V

)

with Respect to GND

2 0V to a7 0V

(1)

Program Voltage with

Respect to GND during
Block Erase Byte Write

2 0V to a14 0V

(1 2)

Supply Voltage

with Respect to GND

2 0V to a7 0V

(1)

Output Short Circuit Current

100 mA

(3)

NOTICE This data sheet contains preliminary infor-
mation on new products in production The specifica-
tions are subject to change without notice Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

NOTES
1 Minimum DC voltage is

0 5V on input output pins During transitions this level may undershoot to

2 0V for periods

20 ns Maximum DC voltage on input output pins is V

0 5V which during transitions may overshoot to V

2 0V

for periods

20 ns

2 Maximum DC voltage on V

may overshoot to

14 0V for periods

20 ns

3 Output shorted for no more than one second No more than one output shorted at a time

OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

Operating Temperature

125

Supply Voltage (10%)

4 75

5 25

DC CHARACTERISTICS

Symbol

Parameter

Notes

Min

Max

Unit

Test Conditions

Input Load Current

1 0

Max

or GND

Output Load Current

Max

OUT

or GND

CCS

Standby Current

1 3

2 0

Max

CE e RP e V

See Figure 8

Max

CE e RP e V

0 2V

CCD

Deep Powerdown

See Figure 9

RP e GND

0 2V

Current

OUT

(RY BY) e 0 mA

CCR

Read Current

Max CE e GND

f e 8 MHz I

OUT

0 mA

CMOS Inputs

Max CE e V

f e 8 MHz I

OUT

0 mA

TTL Inputs

VE28F008

DC CHARACTERISTICS

(Continued)

Symbol

Parameter

Notes

Min

Max

Unit

Test Conditions

CCW

Byte Write Current

Byte Write In Progress

CCE

Block Erase Current

Block Erase In Progress

CCES

Erase Suspend Current

1 2

Block Erase Suspended
CE e V

PPS

Standby Current

200

PPD

Deep Powerdown

RP e GND

0 2V

Current

PPW

Write Current

PPH

Byte Write in Progress

PPE

Block Erase Current

PPH

Block Write in Progress

PPES

Erase Suspend

200

PPH

Current

Block Erase Suspended

Input Low Voltage

0 5

0 8

Input High Voltage

2 0

0 5

Output Low Voltage

0 45

Min

5 8 mA

Output High Voltage

2 4

Min

e b

2 5 mA

PPL

during Normal

0 0

6 5

Operations

PPH

during Erase Write

11 4

12 6

Operations

LKO

Erase Write Lock

1 8

Voltage

CAPACITANCE

(5)

25 C f e 1 MHz

Symbol

Parameter

Typ

Max

Unit

Conditions

Input Capacitance

OUT

Output Capacitance

OUT

NOTES
1 All currents are in RMS unless otherwise noted
2 I

CCES

is specified with the device deselected If the VE28F008 is read while in Erase Suspend Mode current draw is the

sum of I

CCES

and I

CCR

3 Includes RY BY
4 Block Erases Byte Writes are inhibited when V

PPL

and not guaranteed in the range between V

PPH

and V

PPL

5 Sampled not 100% tested

VE28F008

AC INPUT OUTPUT REFERENCE WAVEFORM

271305 � 9

AC test inputs are driven at 3 0V for a Logic ``1'' and 0 0V for a Logic ``0''
Input timing begins and output timing ends at 1 5V Input rise and fall times
(10% to 90%)

10 ns

AC TESTING LOAD CIRCUIT

271305 � 10

30 pF

Includes Jig Capacitance

3 3 kX

AC CHARACTERISTICS

Read-Only Operations

(1 4)

Symbol

Parameter

Notes

VE28F008-95

(4)

Unit

Min

Max

AVAV

Read Cycle Time

AVQV

ACC

Address to Output Display

ELQV

CE to Output Delay

PHQV

PWH

RP High to Output Delay

400

GLQV

OE to Output Delay

ELQX

CE to Output Low Z

EHQZ

CE High to Output High Z

GLQX

OLZ

OE to Output Low Z

GHQZ

OE High to Output High Z

Output Hold from Addresses

CE or OE Change Whichever
is First

NOTES
1 See AC Input Output Reference Waveform for timing measurements
2 OE may be delayed up to t

� t

after the falling edge of CE without impact on t

3 Sampled not 100% tested
4 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics

VE28F008

AC CHARACTERISTICS

Write Operations

(1 7)

Symbol

Parameter

Notes

VE28F008-95

(7)

Unit

Min

Max

AVAV

Write Cycle Time

PHWL

RP High Recovery to WE Going Low

ELWL

CE Setup to WE Going Low

WLWH

WE Pulse Width

VPWH

VPS

Setup to WE Going High

100

AVWH

Address Setup to WE Going High

DVWH

Data Setup to WE Going High

WHDX

Data Hold from WE High

WHAX

Address Hold from WE High

WHEH

CE Hold from WE High

WHWL

WPH

WE Pulse Width High

WHRL

WE High to RY BY Going Low

100

WHQV1

Duration of Byte Write Operation

5 6

WHQV2

Duration of Block Erase Operation

5 6

0 3

sec

WHGL

Write Recovery before Read

QVVL

VPH

Hold from Valid SRD RY BY High

2 6

NOTES
1 Read timing characteristics during erase and byte write operations are the same as during read-only operations Refer to
AC Characteristics for Read-Only Operations
2 Sampled not 100% tested
3 Refer to Table 3 for valid A

for byte write or block erasure

4 Refer to Table 3 for valid D

for byte write or block erasure

5 The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard
Intel flash memory including byte program and verify (byte write) and block precondition precondition verify erase and
erase verify (block erase)
6 Byte write and block erase durations are measured to completion (SR 7

1 RY BY

) V

should be held at

PPH

until determination of byte write block erase success (SR 3 4 5

7 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics

BLOCK ERASE AND BYTE WRITE PERFORMANCE

Parameter

Notes

VE28F008-95

Unit

Min

Typ

Max

Block Erase Time

1 2

1 6

sec

Block Write Time

1 2

0 6

2 1

sec

NOTES
1 25 C 12 0 V

2 Excludes System-Level Overhead

VE28F008

ALTERNATIVE CE-CONTROLLED WRITES

(1)

Symbol

Parameter

Notes

VE28F008-95

(6)

Unit

Min

Max

AVAV

Write Cycle Time

PHEL

RP High Recovery to CE Going Low

WLEL

WE Setup to CE Going Low

ELEH

CE Pulse Width

VPEH

VPS

Setup to CE Going High

100

AVEH

Address Setup to CE Going High

DVEH

Data Setup to CE Going High

EHDX

Data Hold from CE High

EHAX

Address Hold from CE High

EHWH

WE Hold from CE High

EHEL

EPH

CE Pulse Width High

EHRL

CE High to RY BY Going Low

100

EHQV1

Duration of Byte Write Operation

EHQV2

Duration of Block Erase Operation

0 3

sec

EHGL

Write Recovery before Read

QVVL

VPH

Hold from Valid SRD RY BY High

2 5

NOTES
1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where CE
defines the write pulsewidth (within a longer WE timing waveform) all setup hold and inactive WE times should be mea-
sured relative to the CE waveform
2 Sampled not 100% tested
3 Refer to Table 3 for valid A

for byte write or block erasure

4 Refer to Table 3 for valid D

for byte write or block erasure

5 Byte write and block erase durations are measured to completion (SR 7

1 RY BY

) V

should be held at

PPH

until determination of byte write block erase success (SR 3 4 5

6 See AC Input Output Reference Waveforms and AC Testing Load Circuits for testing characteristics

Электронный компонент: 28F008SA-L