Data Sheet Rev. 1.4
1
2001-10-18
5-V Low-Drop Voltage Regulator
TLE 4290
P-TO252-5-1
P-TO263-5-1
P-TO220-5-11
Features
Output voltage 5 V
2%
Very low current consumption
450 mA current capability
Power Good Feature
Very low-drop voltage
Short-circuit-proof
Reverse polarity proof
Suitable for use in automotive electronics
New type
Functional Description
The TLE 4290 is a monolithic integrated low-drop
voltage regulator which can supply loads up to 450 mA
with power good feature. An input voltage up to 42 V is
regulated to
V
Q,nom
= 5.0 V. The device is designed to
supply
-controllers in the severe environment of
automotive applications. Therefore it is protected
against overload, short circuit and over temperature
conditions. Of course the TLE 4290 can been used also
in all other applications, where a stabilized 5 V voltage is
required.
Type
Ordering Code
Package
TLE 4290 D Q67006-A9408
P-TO252-5-1 (SMD)
TLE 4290 G Q67006-A9405
P-TO263-5-1 (SMD)
TLE 4290
Q67000-A9407
P-TO220-5-11
TLE 4290
Data Sheet Rev. 1.4
2
2001-10-18
Power Good
The Power Good PG pin informs e.g. the microcontroller in case the output voltage has
fallen below the lower threshold
V
Q,pgt-d
of typ. 3.65 V. Connecting the regulator to a
battery voltage at first the power good signal remains LOW. When the output voltage has
reached the higher threshold
V
Q,pgt-i
the power good output remains still LOW for the
power good delay time
t
rd
. Afterwards the power good output turns HIGH. The delay time
can be set by the user with an external capacitor at pin D according to the requirements
of the application.
The Power Good circuitry supervises the output voltage. In case
V
Q
falls below the lower
Power Good switching threshold
V
Q,pgt-d
the PG output is set LOW after the Power Good
reaction time. The Power Good LOW signal is generated down to an output voltage
V
Q
to 1 V. A LOW signal at the Power Good pin informs that the battery was lost and
memory is no longer valid.
The feature should be used in combination with a microcontroller with internal reset.
Figure 1
Block Diagram
AEB02823
Current
and
Saturation
Control
Band-
Gap-
Reference
TLE 4290
Power
Good
Control
PG
Q
I
D
GND
1
5
2
4
Data Sheet Rev. 1.4
3
2001-10-18
TLE 4290
Figure 2
Pin Configuration (top view)
Pin Definitions and Functions
Pin No. Symbol Function
1
I
Input; block to ground directly at the IC with a ceramic capacitor.
2
PG
Power Good; open collector output. Add a pull up resistor of > 5 k
to pin Q.
3
GND
Ground; Pin 3 internally connected to heatsink.
4
D
Delay; connect a capacitor to GND for setting power good delay
time.
5
Q
Output; block to ground with a capacitor,
C
22 F
ESR < 5
at 10 kHz.
AEP02827
I
PG
Q
D
GND
AEP02826
GND
PG
I
Q
D
AEP02825
PG
D Q
I
GND
P-TO252-5-1 (D-PAK)
P-TO263-5-1 (SMD)
P-TO220-5-11
TLE 4290
Data Sheet Rev. 1.4
4
2001-10-18
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Input I
Voltage
V
I
42
45
V
Current
I
I
Internally limited
Output Q
Voltage
V
Q
1.0
16
V
Current
I
Q
Internally limited
Power Good Output PG
Voltage
V
PG
0.3
25
V
Current
I
PG
5
5
mA
Delay D
Voltage
V
D
0.3
7
V
Current
I
D
2
2
mA
Temperature
Junction temperature
T
j
40
150
C
Storage temperature
T
stg
50
150
C
Data Sheet Rev. 1.4
5
2001-10-18
TLE 4290
Note: In the operating range, the functions given in the circuit description are fulfilled.
Operating Range
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
Input voltage
V
I
5.5
42
V
Junction temperature
T
j
40
150
C
Thermal Resistance
Junction case
R
thj-c
4
K/W
Junction ambient
R
thj-a
53
K/W TO263
1)
Junction ambient
R
thj-a
78
K/W TO252
1)
Junction ambient
R
thj-a
65
K/W TO220
1)
Worst case, regarding peak temperature; zero airflow; mounted on a PCB FR4, 80
80
1.5 mm
3
, heat sink
area 300 mm
2
TLE 4290
Data Sheet Rev. 1.4
6
2001-10-18
Characteristics
V
I
= 13.5 V; 40
C <
T
j
< 150
C (unless otherwise specified)
Parameter
Symbol
Limit Values
Unit
Measuring
Condition
min.
typ.
max.
Output
Output voltage
V
Q
4.9
5.0
5.1
V
5 mA <
I
Q
< 400 mA;
6 V <
V
I
< 28 V
Output voltage
V
Q
4.9
5.0
5.1
V
5 mA <
I
Q
< 200 mA;
6 V <
V
I
< 40 V
Output current limitation
I
Q
450
700
mA
1)
Current consumption;
I
q
=
I
I
I
Q
I
q
200
230
A
I
Q
= 1 mA;
T
j
= 25
C
Current consumption;
I
q
=
I
I
I
Q
I
q
200
255
A
I
Q
= 1 mA;
T
j
85 C
Current consumption;
I
q
=
I
I
I
Q
I
q
5
12
mA
I
Q
= 250 mA
Current consumption;
I
q
=
I
I
I
Q
I
q
12
25
mA
I
Q
= 400 mA
Drop voltage
V
dr
250
500
mV
I
Q
= 300 mA
V
dr
=
V
I
V
Q
1)
Load regulation
V
Q, lo
30
15
30
mV
V
I
= 6 V;
I
Q
= 5 mA to 400 mA
Line regulation
V
Q, li
15
5
15
mV
V
l
= 8 V to 32 V;
I
Q
= 5 mA
Power supply ripple
rejection
PSRR
60
dB
f
r
= 100 Hz;
V
r
= 0.5 Vpp
Temperature output
voltage drift
0.5
mV/K
Output Capacitor
C
Q
22
F
ESR < 5
in the
operation range
Power Good Output PG and Delay Timing D
Power Good switching
threshold
V
Q,pgt-i
4.45
4.65
4.80
V
V
Q
increasing
dV
Q
dT
-----------
Data Sheet Rev. 1.4
7
2001-10-18
TLE 4290
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at
T
a
= 25
C and
the given supply voltage.
Figure 3
Test Circuit
Power Good switching
threshold
V
Q,pgt-d
3.50
3.65
3.80
V
V
Q
decreasing
Power Good output low
voltage
V
PGL
0.2
0.4
V
R
PG
5 k;
V
Q
> 1 V
Power Good output
leakage current
I
PGH
0
2
A
V
PG
> 4.5 V
Power Good charging
current
I
D,c
3
6
9
A
V
D
= 1 V
Upper timing threshold
V
DU
1.5
1.8
2.2
V
Lower timing threshold
V
DL
0.60
0.85
1.10
V
Power Good delay time
t
rd
10
16
22
ms
C
D
= 47 nF
Power Good reaction time
t
rr
0.2
0.5
2.0
s
C
D
= 47 nF
1)
Measured when the output voltage
V
Q
has dropped 100 mV from the nominal value obtained at
V
I
= 13.5 V.
Characteristics (cont'd)
V
I
= 13.5 V; 40
C <
T
j
< 150
C (unless otherwise specified)
Parameter
Symbol
Limit Values
Unit
Measuring
Condition
min.
typ.
max.
AES02824
TLE 4290
5
2
GND
I
D
C
I2
100 nF
C
I1
1000 F
C
D
47 nF
I
D,C
I
I
V
I
I
Q
R
PG
5 k
V
Q
I
GND
V
PG
C
Q
22 F
Q
PG
I
D
4
1
TLE 4290
Data Sheet Rev. 1.4
8
2001-10-18
Application Information
Figure 4
Application Diagram
Input, Output
An input capacitor is necessary for damping line influences. A resistor of approx. 1
in
series with
C
I
, can damp the LC of the input inductivity and the input capacitor.
The TLE 4290 requires an output capacitor of at least 22
F with an ESR below 5 for
stability.
Power Good
The Power Good pin informs e.g. the micro-controller in case the output voltage has
fallen below a threshold of typ. 3.65 V. When the battery voltage is supplied the Power
Good signal indicates a loss of memory due to missing power. After the Memory Good
switching threshold is reached the Power Good output remains low for the Power Good
delay time. This time can be set by the user with an external capacitor at pin D according
to the requirements of the application, e.g. the time until the microcontroller is initialized
and ready to receive any information.
AES02822
Current
and
Saturation
Control
Band-
Gap-
Reference
TLE 4290
Power
Good
Control
2
5
I
4
C
I1
C
I2
V
BAT
C
D
47 nF
GND
R
PG
5 k
22
F
-Controller
V
CC
NMI /
PORT
Internal
Reset
D
PG
Q
100
nF
C
Q2
C
Q1
1
Data Sheet Rev. 1.4
9
2001-10-18
TLE 4290
The power good circuit supervises the output voltage. In case
V
Q
falls below the Power
Good switching threshold the Power Good output PG is set LOW after the power good
reaction time. The power good LOW signal is generated down to an output voltage
V
Q
to 1 V. A LOW signal at the power good pin informs that the battery was lost and memory
is no longer valid.
The feature should only be used in combination to a microcontroller with internal reset.
For the power good delay time after the output voltage of the regulator is above the reset
threshold, the reset signal is set High again. The reset delay time is defined by the reset
delay capacitor
C
D
at pin D.
The Power Good delay time is defined by the charging time of an external delay
capacitor
C
D
.
C
D
= (
t
rd
I
D,c
) /
V
With
C
D
Power Good delay capacitor
t
rd
Power Good delay time
V
=
V
DU
, typical 1.8 V
I
D,c
Charge current typical 6
A
Figure 5
Power Good Timing
AED03074
Thermal
t
rd
Power-on
Voltage Dip
Secondary
Overload
at Output
Spike
V
DL
V
V
D
V
PG
D, c
=
V
d
dt
V
Q
t
rr
<
rr
t
V
DU
at Input
Undervoltage
Shutdown
C
D
Power Good
Signal
Q,pgt_d
V
Q,pgt_i
V
TLE 4290
Data Sheet Rev. 1.4
10
2001-10-18
The power good reaction time
t
rr
is the time it takes the voltage regulator to set power
good output PG LOW after the output voltage has dropped below the power good
switching threshold. It is typically 0.5
s for delay capacitor of 47 nF. For other values for
C
D
the reaction time can be estimated using the following equation:
t
rr
= 10 ns/nF
C
D
The Power Good output is an open collector output. It requires externally a pull up
resistor of at least 5 k
to Q.
Typical Performance Characteristics
Output Voltage
V
Q
versus
Temperature
T
j
Output Voltage
V
Q
versus
Input Voltage
V
I
AED03033
-40
0
40
80
4.6
j
T
Q
V
V
I
= 13.5 V
4.7
4.8
4.9
5.0
5.1
V
5.2
C 160
120
R
6
4
2
0
4
0
2
8
12
10
Q
V
V
10
V
6
8
V
AED01929
= 25
L
Data Sheet Rev. 1.4
11
2001-10-18
TLE 4290
Output Current
I
Q
versus
Temperature
T
j
Current Consumption
I
q
versus Output Current
I
Q
;
T
j
= 25
C
Output Current
I
Q
versus
Input Voltage
V
I
Current Consumption
I
q
versus Output Current
I
Q
AED03034
-40
0
40
80
120 C 160
0
j
T
200
400
600
800
1000
mA
1200
Q
I
0
0
AED03112
q
0.8
1.6
mA
2.4
= 13.5 V
mA
V
20
40
60
80
120
Q
2.0
0.4
1.2
AED03046
0
10
20
30
40 V 50
0
0.4
0.8
1.2
A
1.0
0.6
0.2
I
V
I
Q
= 125 C
T
j
25 C
0
0
AED03035
q
mA
= 13.5 V
mA
V
100
200
300
400
600
Q
10
20
30
40
50
60
70
80
Data Sheet Rev. 1.4
12
2001-10-18
TLE 4290
Drop Voltage
V
dr
versus
Output Current
I
Q
Upper Timing Threshold
V
DU
versus Temperature
T
j
Charge Current
I
D,c
versus Temperature
T
j
AED01935
0
0
Q
I
100
200
300
400
500
600
700
800
mV
V
dr
j
T
= 125 C
25 C
200
400
600
1000
mA
0
-40
AED03037
V
DU
mA
= 13.5 V
C
V
j
T
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
40
80
120
160
AED03036
-40
0
I
V
= 13.5 V
1
2
3
4
5
6
7
8
A
0
40
80
120
160
C
I
T
j
= 1 V
D
V
D, c
Data Sheet Rev. 1.4
13
2001-10-18
TLE 4290
Package Outlines
P-TO252-5-1 (D-PAK)
(Plastic Transistor Single Outline)
GPT09161
5.4
0.1
-0.10
6.5
+0.15
A
0.5
9.9
6.22
-0.2
1
0.1
0.15
0.8
0.15 max
0.1
per side
5x0.6
1.14
4.56
+0.08
-0.04
0.9
2.3
-0.10
+0.05
B
0.51 min
0.1
1
+0.08
-0.04
0.5
0...0.15
B
A
0.25
M
0.1
All metal surfaces tin plated, except area of cut.
(4.17)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information"
Dimensions in mm
SMD = Surface Mounted Device
TLE 4290
Data Sheet Rev. 1.4
14
2001-10-18
A
8 max.
B
A
0.25
M
0.1
Typical
9.8
0.15
0.2
10
8.5
1)
7.55
1)
(15)
0.2
9.25
0.3
1
0...0.15
5x0.8
0.1
0.1
1.27
4.4
B
0.5
0.1
0.3
2.7
4.7
0.5
0.05
1)
0.1
All metal surfaces tin plated, except area of cut.
2.4
4x1.7
P-TO263-5-1-1 (SMD)
(Plastic Transistor Single Outline)
gp
t
0
911
3_m
a
l
ac
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information"
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet Rev. 1.4
15
2001-10-18
TLE 4290
gpt09064_ma
A
A
0.25
M
Typical
9.8
0.15
2.8
1)
15.65
0.3
12.95
0...0.15
1.7
0.8
0.1
0.1
1.27
4.4
9.25
0.2
0.05
1)
All metal surfaces tin plated, except area of cut.
C
0.2
17
0.3
8.5
1)
10
0.2
3.7
-0.15
C
2.4
0.5
0.1
0.3
8.6
10.2
0.3
0.4
3.9
0.4
8.4
3.7
0.3
P-TO220-5-11
(Plastic Transistor Single Outline)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information"
Dimensions in mm
TLE 4290
Data Sheet Rev. 1.4
16
2001-10-18
Data Sheet Rev. 1.4
17
2001-10-18
TLE 4290
Data Sheet Rev. 1.4
18
2001-10-18
TLE 4290
Edition 2001-10-18
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 Mnchen, Germany
Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe
certain components and shall not be consid-
ered as warranted characteristics.
Terms of delivery and rights to technical
change reserved.
We hereby disclaim any and all warranties,
including but not limited to warranties of
non-infringement, regarding circuits, descrip-
tions and charts stated herein.
Infineon Technologies is an approved CECC
manufacturer.
Information
For further information on technology, deliv-
ery terms and conditions and prices please
contact your nearest Infineon Technologies
Office in Germany or our Infineon Technolo-
gies Representatives worldwide (see ad-
dress list).
Warnings
Due to technical requirements components
may contain dangerous substances. For in-
formation on the types in question please
contact your nearest Infineon Technologies
Office.
Infineon Technologies Components may only
be used in life-support devices or systems
with the express written approval of Infineon
Technologies, if a failure of such components
can reasonably be expected to cause the fail-
ure of that life-support device or system, or to
affect the safety or effectiveness of that de-
vice or system. Life support devices or sys-
tems are intended to be implanted in the hu-
man body, or to support and/or maintain and
sustain and/or protect human life. If they fail, it
is reasonable to assume that the health of the
user or other persons may be endangered.
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