Edition 2005-09-28
Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München

Infineon Technologies AG 1999.

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F3 latched off version

Revision History:

2005-09-28

Datasheet

Previous Version:

V1.0

Page

Subjects (major changes since last revision)

Type

OSC

Package

ICE3BS02L

67kHz

PG-DIP-8-6

Version 1.1

28 Sep 2005

ICE3BS02L

Off-Line SMPS Current Mode Controller
with integrated 500V Startup Cell and
Latched off Mode

test

PG-DIP-8-6

Description

The F3 Controller provides Active Burst Mode to reach the
lowest Standby Power Requirements <100mW at no load. As
the controller is always active during Active Burst Mode, there
is an immediate response on load jumps without any black out
in the SMPS. In Active Burst Mode the ripple of the output
voltage can be reduced <1%. Furthermore, to increase the
robustness and safety of the system, the device enters into
Latched Off Mode in the cases of Overtemperature,
Overvoltage or Short Winding. The Latched Off Mode can only
be reset by disconnecting the main line. Auto Restart Mode is
entered for cases like open loop or overload. By means of an
internal precise peak current limitation, the dimension of the
transformer and the secondary diode can be lowered which leads
to more cost efficiency. An adjustable blanking window
prevents the IC from entering Auto Restart Mode or Active
Burst Mode unintentionally in case of high load jumps.

Product Highlights

· Active Burst Mode to reach the lowest Standby Power

Requirements < 100mW

· Latched Off Mode and Auto Restart Mode to increase

robustness and safety of the system

· Adjustable Blanking Window for high load jumps to

increase system reliability

· PB-free Plating and RoHS compliant

Features

· 500V Startup Cell switched off after Start Up
· Active Burst Mode for lowest Standby Power

@ light load controlled by Feedback Signal

· Fast load jump response in Active Burst Mode
· 67kHz internally fixed switching frequency
· Latched Off Mode for Overtemperature Detection
· Latched Off Mode for Overvoltage Detection
· Latched Off Mode for Short Winding Detection
· Auto Restart Mode for Overload and Open Loop
· Auto Restart Mode for VCC Undervoltage
· Blanking Window for short duration high current
· User defined Soft Start
· Minimum of external components required
· Max Duty Cycle 72%
· Overall tolerance of Current Limiting

< ±5%

· Internal PWM Leading Edge Blanking
· Soft driving for low EMI

SoftS

VCC

Bulk

Converter

DC Output

ICE3BS02L F3

with Latch off Mode

Snubber

Power

Management

PWM Controller

Current Mode

85 ... 270 VAC

Typical Application

Sense

Gate

Startup Cell

Precise Low

Tolerance Peak

Current Limitation

SoftS

GND

VCC

Active Burst Mode

Latched Off Mode

Auto Restart Mode

Control Unit

ICE3BS02L

Table of Contents

Page

Version 1.1

28 Sep 2005

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3

Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4

PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.1

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.2

PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.3

Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.5

Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.5.1

Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.5.2

Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6

Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.6.1

Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.6.2

Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6.2.1

Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6.2.2

Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6.2.3

Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6.3

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.6.3.1

Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.6.3.2

Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3.1

Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3.2

Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3.3

PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.4

Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.5

Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.6

Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Version 1.1

28 Sep 2005

ICE3BS02L

Pin Configuration and Functionality

1.1

Pin Configuration with PG-DIP-8-6

Figure 1

Pin Configuration PG-DIP-8-6(top view)

Note:

Pin 4 and 5 are shorted within the DIP 8 package.

1.2

Pin Functionality

SoftS (Soft Start & Auto Restart Control)
The SoftS pin combines the functions of Soft Start during
Start Up and error detection for Auto Restart Mode. These
functions are implemented and can be adjusted by means of
an external capacitor at SoftS to ground. This capacitor also
provides an adjustable blanking window for high load jumps,
before the IC enters into Auto Restart Mode.

FB (Feedback)
The information about the regulation is provided by the FB
Pin to the internal Protection Unit and to the internal PWM-
Comparator to control the duty cycle. The FB-Signal
controls in case of light load the Active Burst Mode of the
controller.

CS (Current Sense)
The Current Sense pin senses the voltage developed on the
series resistor inserted in the source of the external
PowerMOS. If CS reaches the internal threshold of the
Current Limit Comparator, the Driver output is immediately
switched off. Furthermore the current information is
provided for the PWM-Comparator to realize the Current
Mode.

Gate
The Gate pin is the output of the internal driver stage
connected to the Gate of an external PowerMOS.

HV (High Voltage)
The HV pin is connected to the rectified DC input voltage. It
is the input for the integrated 500V Startup Cell.

VCC (Power supply)
The VCC pin is the positive supply of the IC. The operating
range is between 8.5V and 21V.

GND (Ground)
The GND pin is the ground of the controller.

Pin

Symbol

Function

SoftS

Soft-Start

Feedback

Current Sense

High Voltage Input

Gate

Driver Stage Output

VCC

Controller Supply Voltage

GND

Controller Ground

Package PG-DIP-8-6

GND

SoftS

VCC

Gate

Version 1.1

28 Sep 2005

ICE3BS02L

Representative Blockdiagram

Figure 2

Representative Blockdiagram

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te

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a
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f
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85 .

.
.
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l
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6
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to

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t

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h
er

a
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25k

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wer

-
Down

Res

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Res

e
t

< 6

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ed O

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Leadi

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ki

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n

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V

Unde

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Loc

k
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ut

15V

5
V

t
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t
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t
up C

e
l
l

C6a

32V

C6b

ICE3BS02L

Functional Description

Version 1.1

28 Sep 2005

Functional Description

All values which are used in the functional description are
typical values. For calculating the worst cases the min/max
values which can be found in section 4 Electrical
Characteristics have to be considered.

3.1

Introduction

The F3 is the further development of the F2 to meet the
requirements for the lowest Standby Power at minimum load
and no load conditions. A new fully integrated Standby
Power concept is implemented into the IC in order to keep
the application design easy. Compared to F2 no further
external parts are needed to achieve the lowest Standby
Power. An intelligent Active Burst Mode is used for this
Standby Mode. After entering this mode there is still a full
control of the power conversion by the secondary side via the
same optocoupler that is used for the normal PWM control.
The response on load jumps is optimized. The voltage ripple
on V

out

is minimized. V

out

is further on well controlled in this

mode.
The usually external connected RC-filter in the feedback line
after the optocoupler is integrated in the IC to reduce the
external part count.
Furthermore a high voltage startup cell is integrated into the
IC which is switched off once the Undervoltage Lockout on-
threshold of 15V is exceeded. The external startup resistor is
no longer necessary. Power losses are therefore reduced.
This increases the efficiency under light load conditions
drastically.
The Soft-Start capacitor is also used for providing an
adjustable blanking window for high load jumps. During this
time window the overload detection is disabled. With this
concept no further external components are necessary to
adjust the blanking window.
In order to increase the robustness and safety of the system,
the IC provides 2 levels of protection modes: Latched Off
Mode and Auto Restart Mode. The Latched Off Mode is only
entered under dangerous conditions which can damage the
SMPS if not switched off immediately. A restart of the
system can only be done by disconnecting the AC line.
The Auto Restart Mode reduces the average power
conversion to a minimum under unsafe operating conditions.
This is necessary for a prolonged fault condition which could
otherwise lead to a destruction of the SMPS over time. Once
the malfunction is removed, normal operation is
automatically initiated after the next Start Up Phase.
The internal precise peak current limitation reduces the costs
for the transformer and the secondary diode. The influence
of the change in the input voltage on the power limitation can
be avoided together with the integrated Propagation Delay
Compensation. Therefore the maximum power is nearly
independent on the input voltage which is required for wide
range SMPS. There is no need for an extra over-sizing of the
SMPS, e.g. the transformer or PowerMOS.

3.2

Power Management

Figure 3

Power Management

The Undervoltage Lockout monitors the external supply
voltage V

VCC

. When the SMPS is plugged to the main line

the internal Startup Cell is biased and starts to charge the
external capacitor C

VCC

which is connected to the VCC pin.

This VCC charge current which is provided by the Startup
Cell from the HV pin is 1.05mA. When V

VCC

exceeds the on-

threshold V

CCon

=15V the internal voltage reference and bias

circuit are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power losses
present due to the connection of the Startup Cell to the bus
voltage (HV). To avoid uncontrolled ringing at switch-on a
hysteresis is implemented. The switch-off of the controller
can only take place after Active Mode was entered and V

VCC

falls below 8.5V.
The maximum current consumption before the controller is
activated is about 160

µA.

When V

VCC

falls below the off-threshold V

CCoff

=8.5V the

internal reference is switched off and the Power Down reset
let T1 discharging the soft-start capacitor C

SoftS

at pin SoftS.

Internal Bias

Voltage

Reference

Power Management

Latched Off Mode

Reset

VCC

< 6V

6.5V

Latched Off Mode

Startup Cell

VCC

Undervoltage Lockout

15V

8.5V

Power-Down Reset

SoftS

Active Burst Mode

Auto Restart Mode

Version 1.1

28 Sep 2005

ICE3BS02L

Functional Description

Thus it is ensured that at every startup cycle the voltage ramp
at pin SoftS starts at zero.
The internal Voltage Reference is switched off if Latched
Off Mode or Auto Restart Mode is entered. The current
consumption is then reduced to 300

µA.

Once the malfunction condition is removed, this block will
then turn back on. The recovery from Auto Restart Mode
does not require disconnecting the SMPS from the AC line.
In case Latched Off Mode is entered, VCC needs to be
lowered below 6V to reset the Latched Off Mode. This is
done usually by disconnecting the SMPS from the AC line.
When Active Burst Mode is entered the internal Bias is
switched off in order to reduce the current consumption
below 1.05mA while keeping the Voltage Reference still
active as this is necessary in this mode.

3.3

Startup Phase

Figure 4

Soft Start

At the beginning of the Startup Phase, the IC provides a Soft
Start duration whereby it controls the maximum primary
current by means of a duty cycle limitation. A signal V

SoftS

which is generated by the external capacitor C

Softs

combination with the internal pull up resistor R

SoftS

determines the duty cycle until V

SoftS

exceeds 4V.

When the Soft Start begins, C

SoftS

is immediately charged up

to approx. 1V by T2. Therefore the Soft Start Phase takes

place between 1V and 4V. Above V

SoftsS

= 4V there is no

longer duty cycle limitation DC

max

which is controlled by

comparator C7 since comparator C2 blocks the gate G7 (see
Figure 4). This maximum charge current in the very first
stage when V

SoftS

is below 1V, is limited to 1.32mA.

Figure 5

Startup Phase

By means of this extra charge stage, there is no delay in the
beginning of the Startup Phase when there is still no
switching. Furthermore Soft Start is finished at 4V to have
faster the maximum power capability. The duty cycles DC

and DC

are depending on the mains and the primary

inductance of the transformer. The limitation of the primary
current by DC

is related to V

SoftS

= 4V. But DC

is related

to a maximum primary current which is limited by the
internal Current Limiting with CS = 1V. Therefore the
maximum Startup Phase is divided into a Soft Start Phase
until t1 and a phase from t1 until t2 where maximum power
is provided if demanded by the FB signal.

Soft-Start

Comparator

Soft Start

SoftS

3.25k

6.5V

SoftS

Gate Driver

0.85V

x3.7

PWM OP

max

SoftS

max. Soft Start Phase

5.4V

max. Startup Phase

ICE3BS02L

Functional Description

Version 1.1

28 Sep 2005

3.4

PWM Section

Figure 6

PWM Section

3.4.1

Oscillator

The oscillator generates a fixed frequency. The switching
frequency for ICE3BS02L is f

OSC

= 67kHz. A resistor, a

capacitor and a current source and current sink which
determine the frequency are integrated. The charging and
discharging current of the implemented oscillator capacitor
are internally trimmed, in order to achieve a very accurate
switching frequency. The ratio of controlled charge to
discharge current is adjusted to reach a maximum duty cycle
limitation of D

max

=0.72.

3.4.2

PWM-Latch FF1

The oscillator clock output provides a set pulse to the PWM-
Latch when initiating the external Power Switch conduction.
After setting the PWM-Latch can be reset by the PWM
comparator, the Soft Start comparator or the Current-Limit
comparator. In case of resetting, the driver is shut down
immediately.

3.4.3

Gate Driver

The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents and which is
equipped with a zener diode Z1 (see Figure 7) in order to
improve the control of the Gate attached power transistors as
well as to protect them against undesirable gate
overvoltages.

Figure 7

Gate Driver

The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing the
switch on slope when exceeding the external Power Switch
threshold. This is achieved by a slope control of the rising
edge at the driver's output (see Figure 8).

Figure 8

Gate Rising Slope

Thus the leading switch on spike is minimized. When the
external Power Switch is switched off, the falling shape of
the driver is slowed down when reaching 2V to prevent an
overshoot below ground. Furthermore the driver circuit is
designed to eliminate cross conduction of the output stage.
During powerup when VCC is below the undervoltage
lockout threshold V

VCCoff

, the output of the Gate Driver is

low to disable power transfer to the secondary side.

Oscillator

Duty

Cycle

max

Gate

Driver

0.72

Clock

PWM Section

FF1

Gate

Soft Start

Comparator

PWM

Comparator

Current

Limiting

VCC

PWM-Latch

Gate

Load

= 1nF

ca. t = 130ns

ICE3BS02L

Functional Description

Version 1.1

28 Sep 2005

3.5

Current Limiting

Figure 9

Current Limiting Block

There is a cycle by cycle Current Limiting realized by the
Current-Limit comparator C10 to provide an overcurrent
detection. The source current of the external Power Switch is
sensed via an external sense resistor R

Sense

. By means of

Sense

the source current is transformed to a sense voltage

Sense

which is fed into the pin CS. If the voltage V

Sense

exceeds the internal threshold voltage V

csth

the comparator

C10 immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation is
added to support the immediate shut down without delay of
the Power Switch in case of Current Limiting. The influence
of the AC input voltage on the maximum output power can
thereby be avoided.
To prevent the Current Limiting from distortions caused by
leading edge spikes a Leading Edge Blanking is integrated in
the current sense path for the comparators C10, C12 and the
PWM-OP.
The output of comparator C12 is activated by the Gate G10
if Active Burst Mode is entered. Once activated the current
limiting is thereby reduced to 0.257V. This voltage level
determines the power level when the Active Burst Mode is
left if there is a higher power demand.
A further comparator C11 is implemented to detect
dangerous current levels which could occur if there is a short
winding in the transformer or the secondary diode is shorten.
To ensure that there is no accidentally entering of the

Latched Mode by the comparator C11 a spike blanking with
190ns is integrated in the output path of comparator C11.

3.5.1

Leading Edge Blanking

Figure 10

Leading Edge Blanking

Each time when the external Power Switch is switched on, a
leading edge spike is generated due to the primary-side
capacitances and secondary-side rectifier reverse recovery
time. This spike can cause the gate drive to switch off
unintentionally. To avoid a premature termination of the
switching pulse, this spike is blanked out with a time
constant of t

LEB

= 220ns. During this time, the gate drive will

not be switched off.

3.5.2

Propagation Delay Compensation

In case of overcurrent detection, the switch-off of the
external Power Switch is delayed due to the propagation
delay of the circuit. This delay causes an overshoot of the
peak current I

peak

which depends on the ratio of dI/dt of the

peak current (see Figure 11).

Figure 11

Current Limiting

The overshoot of Signal2 is bigger than of Signal1 due to the
steeper rising waveform. This change in the slope is
depending on the AC input voltage. Propagation Delay
Compensation is integrated to limit the overshoot
dependency on dI/dt of the rising primary current. That
means the propagation delay time between exceeding the
current sense threshold V

csth

and the switch off of the

external Power Switch is compensated over temperature

C11

Current Limiting

C10

1.66V

C12

0.257V

Leading

Edge

Blanking

220ns

G10

Spike

Blanking

190ns

Propagation-Delay

Compensation

csth

Active Burst

Mode

PWM Latch

FF1

10k

1pF

PWM-OP

Latched Off

Mode

Sense

csth

LEB

= 220ns

Sense

Limit

Propagation Delay

Overshoot1

peak1

Signal1

Signal2

Overshoot2

peak2

ICE3BS02L

Functional Description

Version 1.1

28 Sep 2005

within a wide range. Current Limiting is now possible in a
very accurate way.
E.g. I

peak

= 0.5A with R

Sense

= 2. Without Propagation Delay

Compensation the current sense threshold is set to a static
voltage level V

csth

=1V. A current ramp of

dI/dt = 0.4A/µs, that means dV

Sense

/dt = 0.8V/µs, and a

propagation delay time of i.e. t

Propagation Delay

=180ns leads

then to an I

peak

overshoot of 14.4%. By means of propagation

delay compensation the overshoot is only about 2% (see
Figure 12).

Figure 12

Overcurrent Shutdown

The Propagation Delay Compensation is realized by means
of a dynamic threshold voltage V

csth

(see Figure 13). In case

of a steeper slope the switch off of the driver is earlier to
compensate the delay.

Figure 13

Dynamic Voltage Threshold V

csth

3.6

Control Unit

The Control Unit contains the functions for Active Burst
Mode, Auto Restart Mode and Latched Off Mode. The
Active Burst Mode and the Auto Restart Mode are combined

with an Adjustable Blanking Window which is depending on
the external Soft Start capacitor. By means of this Adjustable
Blanking Window, the IC avoids entering into these two
modes accidentally. Furthermore it also provides a certain
time whereby the overload detection is delayed. This delay
is useful for applications which normally works with a low
current and occasionally require a short duration of high
current.

3.6.1

Adjustable Blanking Window

Figure 14

Adjustable Blanking Window

SoftS

is clamped at 4.4V by the closed switch S1 after the

SMPS is settled. If overload occurs V

is exceeding 4.8V.

Auto Restart Mode can't be entered as the gate G5 is still
blocked by the comparator C3. But after V

has exceeded

4.8V the switch S1 is opened via the gate G2. The external
Soft Start capacitor can now be charged further by the
integrated pull up resistor R

SoftS

. The comparator C3 releases

the gates G5 and G6 once V

Softs

has exceeded 5.4V.

Therefore there is no entering of Auto Restart Mode possible
during this charging time of the external capacitor C

SoftS

. The

0,9

0,95

1,05

1,1

1,15

1,2

1,25

1,3

0,2

0,4

0,6

0,8

1,2

1,4

1,6

1,8

with compensation

without compensation

Sense

csth

OSC

Signal1

Signal2

Sense

Propagation Delay

max. Duty Cycle

off time

5.4V

4.8V

1.32V

4.4V

Control Unit

Active

Burst

Mode

Auto

Restart

Mode

SoftS

6.5V

SoftS

ICE3BS02L

Functional Description

Version 1.1

28 Sep 2005

same procedure happens to the external Soft Start capacitor
if a low load condition is detected by comparator C5 when
V

is falling below 1.32V. Only after V

SoftS

has exceeded

5.4V and V

is still below 1.32V Active Burst Mode is

entered.

3.6.2

Active Burst Mode

The controller provides Active Burst Mode for low load
conditions at V

OUT

. Active Burst Mode increases

significantly the efficiency at light load conditions while
supporting a low ripple on V

OUT

and fast response on load

jumps. During Active Burst Mode which is controlled only
by the FB signal the IC is always active and can therefore
immediately response on fast changes at the FB signal. The
Startup Cell is kept switched off to avoid increased power
losses for the self supply.

Figure 15

Active Burst Mode

The Active Burst Mode is located in the Control Unit. Figure
15 shows the related components.

3.6.2.1

Entering Active Burst Mode

The FB signal is always observed by the comparator C5 if
the voltage level falls below 1.32V. In that case the switch S1
is released which allows the capacitor C

SoftS

to be charged

starting from the clamped voltage level at 4.4V in normal
operating mode. If V

SoftS

exceeds 5.4V the comparator C3

releases the gate G6 to enter the Active Burst Mode. The
time window that is generated by combining the FB and
SoftS signals with gate G6 avoids a sudden entering of the
Active Burst Mode due to large load jumps. This time
window can be adjusted by the external capacitor C

SoftS

After entering Active Burst Mode a burst flag is set and the
internal bias is switched off in order to reduce the current
consumption of the IC down to approx. 1.05mA. In this Off
State Phase the IC is no longer self supplied so that therefore
C

VCC

has to provide the VCC current (see Figure 16).

Furthermore gate G11 is then released to start the next burst
cycle once V

has 3.4V exceeded.

It has to be ensured by the application that the VCC remains
above the Undervoltage Lockout Level of 8.5V to avoid that
the Startup Cell is accidentally switched on. Otherwise
power losses are significantly increased. The minimum VCC
level during Active Burst Mode is depending on the load
conditions and the application. The lowest VCC level is
reached at no load conditions at V

OUT

3.6.2.2

Working in Active Burst Mode

After entering the Active Burst Mode the FB voltage rises as
V

OUT

starts to decrease due to the inactive PWM section.

Comparator C6a observes the FB signal if the voltage level
4V is exceeded. In that case the internal circuit is again
activated by the internal Bias to start with switching. As now
in Active Burst Mode the gate G10 is released the current
limit is only 0.257V to reduce the conduction losses and to
avoid audible noise. If the load at V

OUT

is still below the

starting level for the Active Burst Mode the FB signal
decreases down to 3.4V. At this level C6b deactivates again
the internal circuit by switching off the internal Bias. The
gate G11 is released as after entering Active Burst Mode the
burst flag is set. If working in Active Burst Mode the FB
voltage is changing like a saw tooth between 3.4V and 4V
(see Figure 16).

3.6.2.3

Leaving Active Burst Mode

The FB voltage immediately increases if there is a high load
jump. This is observed by comparator C4. As the current
limit is ca. 26% during Active Burst Mode a certain load
jump is needed that FB can exceed 4.8V. At this time C4
resets the Active Burst Mode which also blocks C12 by the

5.4V

4.8V

C6a

4.0V

1.32V

Control Unit

Active

Burst

Mode

4.4V

5k?

Internal Bias

SoftS

6.5V

SoftS

G10

Current

Limiting

C6b

3.4V

G11

ICE3BS02L

Functional Description

Version 1.1

28 Sep 2005

gate G10. Maximum current can now be provided to
stabilize V

OUT

Figure 16

Signals in Active Burst Mode

3.6.3

Protection Modes

The IC provides several protection features which are
separated into two categories. Some enter Latched Off
Mode, the others enter Auto Restart Mode. The Latched Off
Mode can only be reset if VCC is falling below 6V. Both
modes prevent the SMPS from destructive states. The
following table shows the relationship between possible
system failures and the chosen protection modes.

3.6.3.1

Latched Off Mode

Figure 17

Latched Off Mode

The VCC voltage is observed by comparator C1 if 21V is
exceeded. The output of C1 is combined with the output of
C4 which observes FB signal if 4.8V is exceeded. Therefore
the overvoltage detection is only activated if the FB signal is

1.32V

4.00V

4.80V

4.40V

5.40V

SoftS

0.257V

1.00V

8.5V

VCC

1.05mA

VCC

7.2mA

OUT

Max. Ripple < 1%

Blanking Window

Current limit level during
Active Burst Mode

3.40V

Entering Active
Burst Mode

Leaving Active
Burst Mode

VCC Overvoltage

Latched Off Mode

Overtemperature

Latched Off Mode

Short Winding/Short Diode

Latched Off Mode

Overload Auto

Restart

Mode

Open Loop

Auto Restart Mode

VCC Undervoltage

Auto Restart Mode

Short Optocoupler

Auto Restart Mode

21V

Spike

Blanking

8.0us

Thermal Shutdown

>140°C

Latched

Off Mode

VCC

4.8V

C11

1.66V

Spike

Blanking

190ns

Voltage

Reference

Control Unit

Latched Off

Mode Reset

VCC

< 6V

ICE3BS02L

Functional Description

Version 1.1

28 Sep 2005

outside the operating range > 4.8V, e.g. when Open Loop
happens. This means any small voltage overshoots of V

VCC

during normal operating can not start the Latched Off Mode.
The internal Voltage Reference is switched off once Latched
Off Mode is entered in order to reduce the current
consumption of the IC as much as possible. Latched Off
Mode can only be reset by decreasing V

VCC

< 6V. In this

stage, only the UVLO is working which controls the Startup
Cell by switching on/off at V

VCCon

VCCoff

. During this

phase, the average current consumption is only 300

µA. As

there is no longer a self- supply by the auxiliary winding,
VCC drops. The Undervoltage Lockout switches on the
integrated Startup Cell when VCC falls below 8.5V. The
Startup Cell is switched off again when VCC has exceeded
15V. Once the Latched Off Mode was entered, there is no
Start Up Phase after VCC has exceeded the switch-on level
of the Undervoltage Lockout. Therefore VCC changes
between the switch-on and switch-off levels of the
Undervoltage Lockout with a saw tooth shape (see Figure
18).

Figure 18

Signals in Latched Off Mode

The Thermal Shutdown block monitors the junction
temperature of the IC. After detecting a junction temperature
higher than 140°C, Latched Off Mode is entered.
The signals coming from the temperature detection and VCC
overvoltage detection are fed into a spike blanking with a
time constant of 8.0

µs to ensure system reliability.

Furthermore, a short winding or short diode on the secondary
side can be detected by the comparator C11 which is in
parallel to the propagation delay compensated current limit
comparator C10. In normal operating mode comparator C10
keeps the maximum level of the CS signal at 1V. If there is
a failure such as short winding or short diode, C10 is no
longer able to limit the CS signal at 1V. C11 detects then the
over current and enters immediately the Latched Off Mode
to keep the SMPS in a safe stage.

3.6.3.2

Auto Restart Mode

Figure 19

Auto Restart Mode

In case of Overload or Open Loop, FB exceeds 4.8V which
will be observed by C4. At this time S1 is released that V

SoftS

can increase. If V

SoftS

exceeds 5.4V which is observed by C3,

Auto Restart Mode is entered as both inputs of the gate G5
are high. In combining the FB and SoftS signals, there is a
blanking window generated which prevents the system to
enter Auto Restart Mode due to large load jumps. This time
window is the same as for the Active Burst Mode and can
therefore be adjusted by the external C

SoftS

In case of VCC undervoltage, the IC enters into the Auto
Restart Mode and starts a new startup cycle.
Short Optocoupler also leads to VCC undervoltage as there
is no self supply after activating the internal reference and
bias.
In contrast to the Latched Off Mode, there is always a Startup
Phase with switching cycles in Auto Restart Mode. After this
Start Up Phase, the conditions are again checked whether the
failure mode is still present. Normal operation is resumed
once the failure mode is removed that had caused the Auto
Restart Mode.

8.5V

VCCStart

1.05mA

OUT

VCC

15V

5.4V

4.8V

4.4V

Control Unit

Auto

Restart

Mode

SoftS

6.5V

SoftS

Voltage

Reference

ICE3BS02L

Electrical Characteristics

Version 1.1

28 Sep 2005

Electrical Characteristics

Note:

All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not
violated.

4.1

Absolute Maximum Ratings

Note:

Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the
integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is
discharged before assembling the application circuit.

4.2

Operating Range

Note:

Within the operating range the IC operates as described in the functional description.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

HV Voltage

500V

VCC Supply Voltage

VCC

-0.3

FB Voltage

-0.3

6.5

SoftS Voltage

SoftS

-0.3

6.5

Gate Voltage

Gate

-0.3

Internally clamped at 11.5V

CS Voltage

-0.3

6.5

Junction Temperature

-40

150

°C

Storage Temperature

-55

150

°C

Total Power Dissipation

tot

0.9

amb

< 50°C

Thermal Resistance
Junction-Ambient

thJA

K/W

ESD Capability(incl. HV Pin)

ESD

Human body model

According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k

series resistor)

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

VCC Supply Voltage

VCC

VCCoff

Junction Temperature of Controller T

jCon

-25

130

°C

Max value limited due to thermal shut
down of controller

ICE3BS02L

Electrical Characteristics

Version 1.1

28 Sep 2005

4.3

Characteristics

4.3.1

Supply Section

Note:

The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range T

from 25

°C to 130 °C. Typical values represent the median values, which are related to

25°C. If not otherwise stated, a supply voltage of V

= 15 V is assumed.

4.3.2

Internal Voltage Reference

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Start Up Current

VCCstart

160

220

µA

VCC

=14V

VCC Charge Current

VCCcharge1

0.55

1.05

1.60

VCC

= 0V

VCCcharge2

0.88

VCC

=14V

Leakage Current
of Start Up Cell

StartLeak

0.2

µA

VCC

=16V, V

= 450V

Supply Current with
Inactive Gate

VCCsup1

5.5

7.0

Supply Current with Active Gate I

VCCsup2

6.5

8.0

SoftS

= 4.4V

= 0, C

Load

=1nF

Supply Current in
Latched Off Mode

VCClatch

300

µA

= 0

Softs

= 0

Supply Current in
Auto Restart Mode with
Inactive Gate

VCCrestart

300

µA

= 0

Softs

= 0

Supply Current in
Active Burst Mode
with Inactive Gate

VCCburst1

1.05

1.25

VCC

=15V

= 3.7V, V

SoftS

= 4.4V

VCCburst2

0.95

1.15

VCC

= 9.5V

= 3.7V, V

SoftS

= 4.4V

VCC Turn-On Threshold
VCC Turn-Off Threshold
VCC Turn-On/Off Hysteresis

VCCon

VCCoff

VCChys

14.2
8.0
-

15.0
8.5
6.5

15.8
9.0
-

V
V
V

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Trimmed Reference Voltage

REF

6.37

6.50

6.63

measured at pin FB
I

= 0

ICE3BS02L

Electrical Characteristics

Version 1.1

28 Sep 2005

4.3.3

PWM Section

4.3.4

Control Unit

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Fixed Oscillator Frequency

OSC1

kHz

OSC2

kHz

= 25°C

Max. Duty Cycle

max

0.67

0.72

0.77

Min. Duty Cycle

min

< 0.3V

PWM-OP Gain

3.5

3.7

3.9

Voltage Ramp Max Level

Max-Ramp

0.85

Operating Range Min Level

FBmin

0.3

0.7

Operating Range Max level

FBmax

4.75

CS=1V, limited by
Comparator C4

The parameter is not subjected to production test - verified by design/characterization

FB Pull-Up Resistor

SoftS Pull-Up Resistor

SoftS

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Deactivation Level for SoftS
Comparator C7 by C2

SoftSC2

3.85

4.00

4.15

> 5V

Clamped V

SoftS

Voltage during

Normal Operating Mode

SoftSclmp

4.23

4.40

4.57

= 4V

Activation Limit of
Comparator C3

SoftSC3

5.20

5.40

5.60

> 5V

SoftS Startup Current

SoftSstart

1.3

SoftS

= 0V

Over Load & Open Loop Detection
Limit for Comparator C4

FBC4

4.62

4.80

4.98

SoftS

> 5.6V

Active Burst Mode Level for
Comparator C5

FBC5

1.23

1.30

1.37

SoftS

> 5.6V

Active Burst Mode Level for
Comparator C6a

FBC6a

3.85

4.00

4.15

After Active Burst Mode
is entered

Active Burst Mode Level for
Comparator C6b

FBC6b

3.25

3.40

3.55

After Active Burst Mode
is entered

ICE3BS02L

Electrical Characteristics

Version 1.1

28 Sep 2005

Note:

The trend of all the voltage levels in the Control Unit is the same regarding the deviation except V

VCCOVP

and V

VCCPD

4.3.5

Current Limiting

Overvoltage Detection Limit

VCCOVP

> 5V

Latched Thermal Shutdown

jSD

130

140

150

°C

Spike Blanking

Spike

8.0

µs

Power Down Reset for
Latched Mode

VCCPD

4.0

6.0

7.5

After Latched Off Mode
is entered

The parameter is not subjected to production test - verified by design/characterization

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Peak Current Limitation
(incl. Propagation Delay Time of
external MOS)

csth

0.97

1.02

1.07

sense

/ dt = 0.6V/

µs

(see Figure 12)

Peak Current Limitation during
Active Burst Mode

CS2

0.232

0.257

0.282

Leading Edge Blanking

LEB

220

SoftS

= 4.4V

CS Input Bias Current

CSbias

-1.0

-0.2

µA

=0V

Over Current Detection for
Latched Off Mode

CS1

1.570

1.66

1.764

CS Spike Blanking for Comparator

C11

CSspike

190

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

ICE3BS02L

Electrical Characteristics

Version 1.1

28 Sep 2005

4.3.6

Driver Section

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

GATE Low Voltage

GATElow

1.2

VCC

= 5 V

Gate

= 5 mA

1.5

VCC

= 5 V

Gate

= 20 mA

0.8

Gate

= 0 A

1.6

2.0

Gate

= 20 mA

-0.2

0.2

Gate

= -20 mA

GATE High Voltage

GATEhigh

11.5

VCC

= 20V

= 4.7nF

10.5

VCC

= 11V

= 4.7nF

7.5

VCC

= V

VCCoff

+ 0.2V

= 4.7nF

GATE Rise Time

(incl. Gate Rising Slope)

rise

150

Gate

= 2V ...9V

= 4.7nF

Transient reference value

GATE Fall Time

fall

Gate

= 9V ...2V

= 4.7nF

GATE Current, Peak,

Rising Edge

GATE

-0.5

= 4.7nF

The parameter is not subjected to production test - verified by design/characterization

GATE Current, Peak,

Falling Edge

GATE

0.7

= 4.7nF

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Published by Infineon Technologies AG

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