Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

GND

RF-Filter

and

Rectifier

Output

Voltage

ICE

1PD265G

CoolMOS

Controller

Power

Factor Controller + Cool-

MOS: BoostSET
IC for High Power Factor and
low THD

IC for sinusoidal line-current consumption

Controller and CoolMOS within one package

P-DSO-16-10

Power factor achieves nearly 1

Controls boost converter as active harmonic

filter for low THD

Start up with very low current consumption

Zero current detector for discontinuous opera-

tion mode

Output overvoltage protection

Output undervoltage lockout

Internal start up timer

Totem pole output with active shut down

Internal leading edge blanking LEB

Very low comparator and multiplier offsets for

universal input applications

High sophisticated amplifier minimizes distor-

tion inteferences caused by MOSFET switching

The ICE1PD265G IC controls a boost converter
in a way that sinusoidal current is taken from
the single phase line supply and stabilized DC
voltage is available at the output. CoolMOS and
controller are placed together in one package.
This active harmonic filter limits the harmonic
currents resulting from the capacitor pulsed
charge currents during rectification. The power
factor which descibes the ratio between active
and apparent power is almost one. Line voltage
fluctuations can be compensated very effi-
ciently

Type

Ordering Code

Package

ICE1PD265G

P-DSO-16-10

Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

Pin Connections

Pin Description

Pin1,16 GND (Ground)
The GND pins are internally connected via the lead frame

Pin 2 VSENSE (voltage amplifier inverting input)
VSENSE is connected via a resistive divider to the boost converter output. With a capacitor connected to
VAOUT the internal error amplifier acts as an integrator.

Pin 3 VAOUT (voltage amplifier output)
VAOUT is connected internally to the first multiplier input. To prevent overshoot the input voltage is
clamped internally at 5V. Input voltage less then 2.2V shuts the gate driver down. If the current flowing into
this pin is exceeding an internal threshold the multiplier output voltage is reduced to prevent the
MOSFET from overvoltage damage.

Pin 4 MULTIN (multipier input)
MULTIN is the second multiplier input and is connected via a resistive divider to the rectifier output voltage.

Pin 5, 12
not connected

Pin 6,7,8,9,10,11 DRAIN (drain connection of internal CoolMOS)
The DRAIN pins are internally connected via the leadframe. Be aware of 650V input voltage!

Symbol

Function

GND

Ground

VSENSE

Voltage amplifier inverting input

VAOUT

Voltage amplifier output

MULTIN

Multiplier input

n.c.

DRAIN

650V Drain

DRAIN

650V Drain

DRAIN

650V Drain

DRAIN

650V Drain

DRAIN

650V Drain

DRAIN

650V Drain

n.c.

ISENSE

Current sense input + Source

VCC

Positive voltage supply

DETIN

Zero current detector input

GND

Ground

1 GND

2 VSENSE

3 VAOUT

4 MULTIN

16 GND

15 DETIN

14 VCC

13 ISENSE

6 DRAIN

7 DRAIN

8 DRAIN

9 DRAIN

10 DRAIN

11 DRAIN

P-DSO-16-10

5 n.c.

12 n.c.

Do not touch DRAIN pins on

application board: 650V

Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

0.2V

Reference

Voltage

Gate

Drive

Voltage

Amp

Multiplier

Flip-Flop

UVLO

LEB

Restart

Timer

Detector

VSENSE

VAOUT

MULTIN

ISENSE

DETIN

VCC

GND

Current

Comp

multout

Inhibit

time delay

2.2V

2.5V

uvlo

active

shut down

1.5

1.0

12.5V

10V

dVA

=2us

res

=150
us

LEB

=150ns

dsd

=70n

20V

clamp

detin

Inhibit

Enable

OVR

Cool

MOS

DRAIN

20k

10p

Pin 13 ISENSE (current sense input and CoolMOS source)
Controller current sense input and CoolMOS source are internaly connected via bonds.
ISENSE should be connected to an external sense resistor controlling the CoolMOS source current. The input
is internally clamped at -0.3V to prevent negative input voltage interaction. A leading edge blanking circuitry
suppresses voltage spiks when turning the MOSFET on.

Pin 14 Vcc (Positive voltage supply)
If Vcc exceeds the turn-on threshold the IC is switched on. When Vcc falls below the turn-off threshold it is
switched off and power consumption is very low. An auxilliary winding is charging a capacitor which provides
the supply current. A second 100nF ceramic capacitor should be added to Vcc to absorbe supply current
spikes required to charge the MOSFET gate capacitance.

Pin 15 DETIN (Zero current detector input)
DETIN is connected to an auxiliary winding monitoring the zero crossing of the inductor current.

Block Diagram

Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

Functional Description

Introduction

Conventional electronic ballasts and switching power supplies are designed with a bridge rectifier
and a bulk capacitor. Their disadvantage is that the circuit draws power from the line when the
instantaneous AC voltage exceeds the capacitors voltage. This occurs near the line voltage peak
and causes a high charge current spike with following characteristics: The apparent power is higher
than the real power that means low power factor condition, the current spikes are non sinusoidal
with a high content of harmonics causing line noise, the rectified voltage depends on load condition
and requires a large bulk capacitor, special efforts in noise suppression are necessary.

With the ICE1PD265G preconverter a sinusoidal current is achieved which varies in direct instanta-
neous proportional to the input voltage half sine wave and so provides a power factor near 1. This is
due to the appearence of almost any complex load like a resistive one at the AC line. The harmonic
distortions are reduced and comply with the IEC555 standard requirements.

Description

The ICE1PD265G contains a wide bandwidth voltage amplifier used in a feedback loop, an overvolt-
age regulator, an one quadrant multiplier with a wide linear operating range, a current sense compa-
rator, a zero current detector, a PWM and logic circuitry, a totem-pole MOSFET driver, an internal
trimmed voltage reference, a restart timer, an undervoltage lockout circuitry and last not least a
CoolMOS transistor.

Voltage Amplifier

With an external capacitor between VSENSE and VAOUT the voltage amplifier forms an integrator.
The integrator monitors the average output voltage over several line cycles. Typically the integrators
bandwidth is set below 20 Hz in order to suppress the 100 Hz ripple of the rectified line voltage. The
voltage amplifier is internally compensated and has a gain bandwidth of 3 MHz and a phase margin
of 80 degrees. The non-inverting input is biased internally at 2.5V. The output is directly connected
to the multiplier input.
The gate drive is disabled when VSENSE voltage is less than 0.2 V or VAOUT voltage is less than
2.2 V.
If the MOSFET is placed nearby the controller switching inteferences have to be taken into account.
The output of the voltage amplifier is designed in a way to minimize these inteferences.

Overvoltage Regulator

Because of the integrators low bandwidth fast changes of the output voltage can't be regulated
whithin an adequate time. Fast output changes occure during initial start-up, sudden load removal,
or output arcing. While the integrators differential input voltage remains zero during this fast
changes a peak current is flowing through the external capacitor into pin VAOUT. If this current
exceeds an internal defined margin the overvoltage regulator circuitry reduces the multiplier output
voltage. As a result the on time of the MOSFET is reduced.

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ICE1PD265G

Infineon Tech

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10.09.01

Multiplier

The one quadrant multiplier regulates the gate driver with respect of the DC output voltage and the
AC half wave rectified input voltage. Both inputs are designed to achieve good linearity over a wide
dynamic range to represent an AC line free from distortion. Special efforts are made to assure uni-
versal line applications with respect to a 90 to 270 V AC range.
The multiplier output is internally clamped at 1.0V. So the MOSFET is protected against critical
operating during start up.

Current sense comparator, LEB and RS Flip-Flop

An external sense resistor transferes the source current of the MOSFET into a sense voltage.The
multiplier output voltage is compared with this sense voltage.
To protect the current comparator input from negative pulses a current source is inserted which
sends current out of the ISENSE pin every time when ISENSE is falling below ground potential. The
switch-on current peak of the MOSFET is blanked out via a resistor-capacitor circuit with a blanking
time of typically 220ns. Therefore better THD is achieved at low load conditions.
The RS Flip-Flop ensures that only one single switch-on and switch-off pulse appears at the gate
drive output during a given cycle (double pulse suppression).

Zero Current Detector

The zero current detector senses the inductor current via an auxiliary winding and ensures that the
next on-time of the MOSFET is initiated immediately when the inductor current has reached zero.
This diminishes the revers recovery losses of the boost converter diode. The MOSFET is switched
off when the voltage drop of the shunt resistor reaches the voltage level of the multipler output. So
the boost current waveform has a triangular shape and there are no deadtime gaps between the
cycles. This leads to a continuous AC line current limiting the peak current to twice of the average
current.
To prevent false tripping the zero current detector is designed as a Schmitt-Trigger with a hysteresis
of 0.5V. An internal 5V clamp protects the input from overvoltage breadkdown, a 0.6V clamp pre-
vents substrate injection. An external resistor has to be used in series with the auxiliary winding to
limit the current through the clamps.

Restart Timer

If the MOS is off for more than 150us a restart impulse is generated by the restart timer.

Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

Undervoltage Lockout

An undervoltage lockout circuitry switches the IC on when Vcc reaches the upper threshold V

CCH

and switches the IC off when Vcc is falling below the lower threshold V

CCL

. During start up the sup-

ply current is less then 100uA.
An internal voltage clamp has been added to protect the IC from Vcc overvoltage condition. When
using this clamp special care must be taken on power dissipation.
Start up current is provided by an external start up resistor which is connected from the AC line to
the input supply voltage Vcc and a storage capacitor which is connected from Vcc to ground. Be
aware that this capacitor is discharged befor the IC is plugged into the application board. Otherwise
the IC can be destroyed due to the high capacitor voltage.
Bootstrap power supply is created with the previous mentioned auxiliary winding and a diode (see
application circuit).

CoolMOS

The CoolMOS is designed for very low R

DSon

to reduce power dissipation.

Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

Absolute maximum ratings

Parameter

Symbol Min

Max

Unit Remark

Supply + Zener Current

Icc+Iz

Supply Voltage

-0.3

Vz=Zener Voltage
Icc+Iz=20mA

Voltage at Pin 2,4,13

-0.3

6.5

Current into Pin 3

VAOUT

-10

mA
mA

VAOUT=4V,VSENSE=2.8V
VAOUT=0V,VSENSE=2.3V
t<1ms

Current into Pin 15

DETIN

-10

mA
mA

DETIN > 6V
DETIN< 0.4V

Voltage at Pin 6- 11

DRAIN

650

=115�C

Continuous Drain Current

3.2
2

A
A

=25�C

=100�C

Avalanche Energy

0.2

repetitive

ESD Protection

2000

MIL STD 883C method
3015.6, 100pF,1500

Storage Temperature

stg

-50

150

�C

Operating Junction Temper-
ature

-25

150

�C

Thermal Resistance
Junction-Ambient

thJA

120

K/W

P-DSO-16-10

Infineon Technologies

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ICE1PD265G

Infineon Tech

PCI Group

10.09.01

Characteristics

Unless otherwise stated, -40�C<T

<150 �C, V

= 14.5V

Parameter

Symbol

min. typ.

max.

Unit

Test Condition

Start-Up circuit

Zener Voltage

Icc+Iz=18mA

Start-up supply current

CCL

100

Vcc=10V

Operating supply current

CCH

Output low

Vcc Turn-ON threshold

12.5

Vcc Turn-OFF threshold

OFF

9.5

10.5

Vcc Hysteresis

CCHY

2.5

Voltage Amplifier

Voltage feedback Input
Threshold

2.45

2.5

2.55

Pin1 connected with Pin2

Line regulation

FBLR

=12V to 16V

Open Loop Voltage Gain1) G

100

Unity Gain Bandwidth1)

MHz

Phase Margin1)

Degr

Bias current VSENSE

BVSENSE

-1.0

-0.3

Enable Threshold

VSENSEE

0.2

Inhibit Threshold Voltage

VAOUTI

2.2

ISENSE

= -0.1V

Inhibit Time Delay

dVA

ISENSE

= -0.1V

Output Current Source

VAOUTH

-6

VAOUT=0V
VSENSE=2.3V,t<1ms

Output Current Sink

VAOUTL

VAOUT=4V
VSENSE=2.8V, t<1ms

Upper Clamp Voltage

VAOUTH

5.4

VSENSE=2.3V, I= -0.2mA

Lower Clamp Voltage

VAOUTL

1.1

VSENSE=2.8V, I=0.5mA

Overvoltage Regulator

Threshold Current

OVR

Tj=25�C

1) not tested, guaranteed by design

Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

Current Comparator

Input Bias Current

BISENSE

-1

Input Offset Voltage

ISENSEO

150

mV
mV

MULTIN

=0V, VAOUT=2.4V

MULTIN

=0V, VAOUT>2.8V

Max Threshold Voltage

ISENSEM

0.95

1.0

1.05

Threshold at OVR

ISENOVR

0.05

OVR

=50uA

Shut Down Delay

dISG

100

Leading Edge Blanking

LEB

220

Detector

Upper threshold voltage

DETINU

1.5

Lower threshold voltage

DETINL

Hysteresis

DETINHY

0.5

Input current

BDETIN

-1

Input clamp voltage
High state
Low state

DETINHC

DETINLC

0.5

DETIN

=5mA

DETIN

=-5mA

Multiplier

Input bias current

BMULTIN

-1

Dynamic voltage range
MULTIN

MULTIN

0 to 4

VAOUT

=2.75V

Dynamic voltage range
VAOUT

VAOUT

MULTIN

=1V

Multiplier Gain

low

high

0.18
0.56

V
V

VAOUT

<3V

VAOUT

>3.5V

Restart Timer

restart time

RES

150

Parameter

Symbol

min. typ.

max.

Unit

Test Condition

Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

CoolMOS

Drain source breakdown
voltage

BRDSS

600
650

V
V

=25�C

=115�C

Drain source on-resist-
ance

DSon

1.1

1.4
3.8

Ohm
Ohm

=25�C

=150�C

Zero gate voltage drain
current

DSS

0.5

1
70

uA
uA

=0V, T

=25�

=0V, T

=150�

Output capacitance 1)

OSS

150

=25V, f=1MHz

Rise time
Fall time

rise

fall

30
50

ns
ns

1) not tested, guaranteed by design

Parameter

Symbol

min. typ.

max.

Unit

Test Condition

Infineon Technologies

preliminary

ICE1PD265G

Infineon Tech

PCI Group

10.09.01

Electrical Diagrams

Diagram 1: Icc versus Vcc

0,5

1,5

2,5

3,5

4,5

Vcc/V

I
cc /

CC ON

CC OFF

Diagram 2: V

CCON/OFF

versus

Temperature

-40

120

160

Tj / �C

Vcc / V

CC ON

CC OFF

Diagram 4: I

CCL

versus

Temperature, V

=9V

-40

120

160

Tj / �C

CCL

/ uA

Diagram 3: Iccl versus Vcc

Vcc / V

Iccl / u

Infineon Technologies

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ICE1PD265G

Infineon Tech

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10.09.01

Diagram 5: V

vers. Temperature

(pin1 connected to pin2)

2,45

2,46

2,47

2,48

2,49

2,5

2,51

2,52

2,53

2,54

2,55

-40

120

160

Tj / �C

/ V

Diagram 7: Overvoltage Regulator

ISENSE

vers. Threshold Voltage

0,2

0,4

0,6

0,8

1,2

Iovp / uA

I
SEN

/ V

VAOUT

= 3.5V

MULTIN

= 3.0V

Diagram 6: Voltage Amplifier

Open loop gain and Phase

100

120

0,01

0,1

100

1000 10000

f/kHz

100

120

140

160

180

Phi/deg

/dB

Phi

Diagram 8: I

OVR

versus

Temperature

-40

120

160

Tj/�C

OVR

/uA

Infineon Technologies

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ICE1PD265G

Infineon Tech

PCI Group

10.09.01

Diagram 10: Leading edge

blanking (min on-time) vs. Temp.

100

150

200

250

300

-40

120

160

Tj / �C

LEB / ns

Diagram 12: Current sense

threshold V

ISENSE

versus V

VAOUT

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

2,5

3,5

4,5

VAOUT

/ V

I
SENSE

/ V

1.0

1.5

2.0

3.0

Vmultin=4.0

0.5

0.25

Diagram 9: max Threshold

Voltage V

ISENSEM

vs. Temperature

0,95

0,96

0,97

0,98

0,99

1,01

1,02

1,03

1,04

1,05

-40

120

160

Tj/�C

VISEN

SEM/V

Diagram 11: Current Sense

Threshold V

ISENSE

versus V

MULTIN

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

MULTIN

/ V

I
SEN

/ V

VAOUT

=2.75V

3.0V

3.25V

3.5V

4.0V

4.5V

Электронный компонент: ICE1PD265G