Key Features
Applications
4-Pin
4-Pin
P V
P V
olt
olt
ag
ag
e Super
e Super
visor
visor
wit
wit
h Manual R
h Manual R
eset
eset
x
Computers and controllers
x
Embedded controllers
x
Battery operated systems
x
Intelligent instruments
x
Wireless communication systems
x
PDAs and handheld equipment
x
Improved Maxim MAX811/MAX812 replacement
--
Specified to 105C
--
New 4.0V threshold option
x
6
A supply current
x
Monitor 5V, 3.3V and 3V supplies
x
Manual reset input
x
140ms min. reset pulse width
x
Guaranteed over temperature
x
Active-LOW reset valid with 1.1V supply
(IMP811)
x
Small 4-pin SOT-143 package
x
No external components
x
Power-supply transient-immune design
Block Diagrams
IMP811
(IMP812)
VCC
VCC
VCC
GND
GND
RESET
(RESET)
Manual
Reset
MR
811/12_01.eps
C or
P
RESET
Input
The IMP811/IMP812 are low-power supervisors designed to monitor
voltage levels of 3.0V, 3.3V and 5.0V power supplies in low-power
microprocessor (P), microcontroller (C) and digital systems. Each fea-
tures a debounced manual reset input. The IMP811/812 are improved
drop-in replacements for the Maxim MAX811/812 with extended
temperature specifications to 105C.
A reset signal is issued if the power supply voltage drops below a preset
threshold and is asserted for at least 140ms after the supply has risen
above the reset threshold. The IMP811 has an active-low output RESET
that is guaranteed to be in the correct state for V
CC
down to 1.1V. The
IMP812 has an active-high output RESET. The reset comparator is
designed to ignore fast transients on V
CC
.
Low power consumption makes the IMP811/IMP812 ideal for use in
portable and battery-operated equipment. Available in a compact 4-pin
SOT143 package, the devices use minimal board space.
Six voltage thresholds are available to support 3V to 5V systems:
IMP8
IMP8
1
1
1
1
, IMP8
, IMP8
1
1
2
2
P
OWER
M
ANAGEMENT
Reset Threshold
Suffix
Voltage (V)
L
4.63
M
4.38
J
4.00
T
3.08
S
2.93
R
2.63
IMP, Inc.
San Jose, CA
408-432-9100/www.impweb.com
2
IMP8
IMP8
1
1
1
1
, IMP8
, IMP8
1
1
2
2
Ordering Information
Pin Configuration
IMP811
(IMP812)
GND
(RESET) RESET
V
CC
4
MR
3
2
1
811/12_02.eps
SOT143
Package Marking
2
Part Number
1
Reset Threshold (V)
Temperature Range
Pin-Package
(XX Lot Code)
IMP811 Active LOW Reset with Active LOW Manual Reset
IMP811LEUS-T
4.63
40C to +105C
4-SOT143
AMXX
IMP811MEUS-T
4.38
40C to +105C
4-SOT143
ANXX
IMP811JEUS-T
4.00
40C to +105C
4-SOT143
AOXX
IMP811TEUS-T
3.08
40C to +105C
4-SOT143
APXX
IMP811SEUS-T
2.93
40C to +105C
4-SOT143
AQXX
IMP811REUS-T
2.63
40C to +105C
4-SOT143
ARXX
IMP812 Active HIGH Reset with Active LOW Manual Reset
IMP812LEUS-T
4.63
40C to +105C
4-SOT143
ASXX
IMP812MEUS-T
4.38
40C to +105C
4-SOT143
ATXX
IMP812JEUS-T
4.00
40C to +105C
4-SOT143
AUXX
IMP812TEUS-T
3.08
40C to +105C
4-SOT143
AVXX
IMP812SEUS-T
2.93
40C to +105C
4-SOT143
AWXX
IMP812REUS-T
2.63
40C to +105C
4-SOT143
AXXX
2
Pin Terminal Voltage with Respect to Ground
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to 6.0V
RESET,
R
E
S
E
T and
M
R . . . . . . . . . . . . . . . . . 0.3V to (V
CC
+ 0.3V)
Input Current at V
CC
and
M
R . . . . . . . . . . . 20mA
Output Current: RESET or
R
E
S
E
T . . . . . . 20mA
Rate of Rise at V
CC
. . . . . . . . . . . . . . . . . . . . 100V/s
Power Dissipation (T
A
= 70
C) . . . . . . . . . . 320mW
(Derate SOT-143 4mW/C above 70
C)
Operating Temperature Range . . . . . . . . . . 40C to 105C
Storage Temperature Range . . . . . . . . . . . . . 65C to 160C
Lead Temperature (soldering, 10 sec) . . . . . 300C
These are stress ratings only and functional operation is not implied.
Exposure to absolute maximum ratings for prolonged time periods may
affect device reliability
Notes:
1. Tape and Reel packaging is indicated by the -T designation.
2. Devices may also be marked with full part number: 811L, 812M etc. XX refers to lot.
Absolute Maximum Ratings
3
IMP8
IMP8
1
1
1
1
, IMP8
, IMP8
1
1
2
2
Parameter
Symbol Conditions
Min
Typ
Max
Units
Input Voltage (V
CC
) Range
V
CC
T
A
= 0C to 70C
1.1
5.5
V
T
A
= 40C to 105C
1.2
5.5
Supply Current (Unloaded)
I
CC
T
A
= 40C to 85C
V
CC
< 5.5V, L/M/J
6
15
A
T
A
= 40C to 85C
V
CC
< 3.6V, R/S/T
5
10
T
A
= 85C to 105C
V
CC
< 5.5V, L/M/J
25
T
A
= 85C to 105C
V
CC
< 3.6V, R/S/T
20
Reset Threshold
V
TH
L devices
T
A
= 25C
4.56
4.63
4.70
V
T
A
= 40C to 85C
4.50
4.75
T
A
= 85C to 105C
4.40
4.86
M devices
T
A
= 25C
4.31
4.38
4.45
T
A
= 40C to 85C
4.25
4.50
T
A
= 85C to 105C
4.16
4.56
J devices
T
A
= 25C
3.93
4.00
4.06
T
A
= 40C to 85C
3.89
4.10
T
A
= 85C to 105C
3.80
4.20
T devices
T
A
= 25C
3.04
3.08
3.11
T
A
= 40C to 85C
3.00
3.15
T
A
= 85C to 105C
2.92
3.23
S devices
T
A
= 25C
2.89
2.93
2.96
T
A
= 40C to 85C
2.85
3.00
T
A
= 85C to 105C
2.78
3.08
R devices
T
A
= 25C
2.59
2.63
2.66
T
A
= 40C to 85C
2.55
2.70
T
A
= 85C to 105C
2.50
2.76
Reset Threshold Temp. Coefficient
TC
VTH
30
ppm/C
V
CC
to Reset Delay
V
CC
= V
TH
to (V
TH
- 125mV), L/M/J devices
40
s
V
CC
= V
TH
to (V
TH
- 125mV), R/S/T devices
20
Reset Active Timeout Period
V
OL
T
A
= 0C to 70C
140
560
ms
T
A
= 40C to 105C
100
840
MR Minimum Pulse Width
t
MR
10
s
MR Glitch Immunity
Note 3
100
ns
MR to RESET Propagation Delay
t
MD
Note 2
0.5
s
MR Input Threshold
V
IH
V
CC
> V
TH (MAX)
, IMP811/812L/M/J
2.3
V
V
IL
0.8
V
IH
V
CC
> V
TH (MAX)
, IMP811/812R/S/T
0.7V
CC
V
IL
0.25V
CC
MR Pull-up Resistance
10
20
30
k
Low RESET Output Voltage
(IMP811)
V
OL
V
CC
= V
TH
min., I
SINK
= 1.2mA, IMP811R/S/T
0.3
V
V
CC
= V
TH
min., I
SINK
= 3.2mA, IMP811L/M/J
0.4
V
CC
> 1.1V, I
SINK
= 50A
0.3
High RESET Output Voltage
(IMP811)
V
OH
V
CC
> V
TH
max., I
SOURCE
= 500A, IMP811R/S/T
0.8V
CC
V
V
CC
> V
TH
max., I
SOURCE
= 800A, IMP811L/M/J V
CC
-1.5
Low RESET Output Voltage
(IMP812)
V
OL
V
CC
= V
TH
max., I
SINK
= 1.2mA, IMP812R/S/T
0.3
V
V
CC
= V
TH
max., I
SINK
= 3.2mA, IMP812L/M/J
0.4
High RESET Output Voltage
(IMP812)
V
OH
1.8V < V
CC
< V
TH
min., I
SOURCE
= 150A
0.8V
CC
V
Electrical Characteristics
Unless otherwise noted V
CC
is over the full voltage range, T
A
= 40C to 105C.
Typical values at T
A
= 25C, V
CC
= 5V for L/M/J devices, V
CC
= 3.3V for T/S devices and V
CC
= 3V for R devices.
Notes:
1. Production testing done at T
A
= 25C. Over temperature specifications guaranteed by design only using six sigma design limits.
2.
R
E
S
E
T output is active LOW for the IMP811 and RESET output is active HIGH for the IMP812.
3. Glitches of 100ns or less typically will not generate a reset pulse.
4
IMP8
IMP8
1
1
1
1
, IMP8
, IMP8
1
1
2
2
Pin Descriptions
Pin Number
Name
Function
1
GND
Ground
2
RESET
RESET is asserted LOW if V
CC
falls below the reset threshold and remains LOW for the
(IMP811)
140ms minimum after the reset conditions are removed. In addition, RESET is active LOW
as long as the manual reset is low.
2
RESET
RESET is asserted HIGH if V
CC
falls below the reset threshold and remains HIGH for the
(IMP812)
140ms minimum after the reset conditions are removed. In addition, RESET is active
HIGH as long as the manual reset is low.
3
MR
Manual Reset Input. A logic LOW on MR asserts RESET. RESET remains active as long
as MR is LOW and for 180ms after MR returns HIGH. The active low input has an internal
20k
pull-up resistor. The input should be left open if not used. It can be driven by TTL or
CMOS logic or shorted to ground by a switch..
4
V
CC
Power supply input voltage (3.0V, 3.3V, 5.0V)
Related Products
IMP809
IMP810
IMP811
IMP812
Max. Supply Current
15A
15A
15A
15A
Package Pins
3
3
4
4
Manual RESET input
s
s
Package Type
SOT-23
SOT-23
SOT-143
SOT-143
Active-HIGH RESET output
s
s
Active-LOW RESET output
s
s
IMP8
IMP8
1
1
1
1
, IMP8
, IMP8
1
1
2
2
Detailed Description
Reset Timing and Manual Reset (MR)
The reset signal is assertedLOW for the IMP811 and HIGH for
the IMP812 when the V
CC
signal falls below the threshold trip
voltage and remains asserted for 140ms minimum after the V
CC
has risen above the threshold.
A logic low on MR asserts RESET LOW on the IMP811 and HIGH
on the IMP812. MR is internally pulled high through a 20k
resistor and can be driven by TTL/CMOS gates or with open
collector/drain outputs. MR can be left open if not used.
MR may be connected to a normally-open switch connected to
ground without an external debounce circuit.
For added noise rejection, a 0.1F capacitor from MR to Ground
can be added.
Figure 1. Reset Timing and Manual Reset (MR)
5V
0V
5V
0V
V
CC
V
TH
MR
140ms
minimum
Active Reset
Timeout Period
Active Reset
Timeout Period
5V
0V
RESET
5V
0V
RESET
IMP811
IMP812
811/12_03.eps
5
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