TECHNICAL DATA
IN1307
CMOS
IC of Real Time Watch
with Serial Interface, 56 8 RAM
Functions and Features
Count of seconds, minutes, hours, week days, date,
months and years with consideration of the leap years
(before 2100);
56 bytes of the power self-sufficient RAM for the data
storage;
Two-wire consecutive interface;
Programmable rectangular output signal;
Automatic determination of the supply voltage drop and
the switching diagram;
Consumption of less than 500 n in the back-up supply
mode with the operating generator.
Description
icrocircuit IN1307 is essentially the binary decimal digital watch with a calendar, it has the
additional 56 bytes of the power self-sufficient static RAM and possesses the low power
consumption. The addresses and data are applied consecutively via the two-wire bi-directional bus.
The microcircuit is intended for count of the real time in hours, minutes and seconds, count of week
days, date, month and year. The last day of the month is automatically adjusted for the months of
less, than 31 days, including correction for the leap year. The watches function in the 24-hour format
or in the 12-hour format with the AM / PM-indicator. Microcircuit IN1307 has the built-in power
supply control circuit, which determines the supply disruption and automatically switches over the
device into the battery mode.
Designation of Pins
Number of
Package Pin
Identification Type Pin Designation
1
X1
In
Pin for connection of the quartz resonator
2
X2
In
Pin for connection of the quartz resonator
3
VBAT
In
Pin for battery
4 GND
In
Ground
pin
5
SDA
Bi
Input / output of serial data
6
SCL
In
Input of the consecutive cycle signal
7
SQW/OUT
Out
Output of rectangular signal
8 VCC
In
Power
supply
pin
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TECHNICAL DATA
Structural Diagram IN1307
IN1307 Operating Temperatures Range
Operating temperatures range of the microcircuit IN1307:
= - 40 ... + 85
.
IN1307 Limit Mode
Limit and limit permissible operational modes of the microcircuit IN1307 are listed in the Table
Norm
Limit Permissible
Limit
Parameter Description,
Measurement Unit
Identification
min max min max
Supply voltage, V
V
4,5 5,5 -0,5 7,0
Battery voltage, V
V
BAT
2,0 3,5 -0,5 7,0
Low level input voltage, V
V
IL
-0,3 0,8 -0,5 7,0
High level input voltage, V
V
IH
2,2 V
CC
+ 0,3
-0,5
7,0
Storage temperature,
T
S
- - -55
+125
All voltages are indicated relative to ground. Under influence of the limit mode serviceability of
the microcircuits is not guaranteed. After measuring the limit mode serviceability is guaranteed
in the limit permissible mode.
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TECHNICAL DATA
Electric Parameters of IN1307
Electric parameters of the microcircuit IN1307
(
= 40...+ 85
, V
CC
= 4,5 5,5 V )
Norm
Parameter Description,
Measurement Unit
Identification
Measurement
Mode
min max
Input leakage current, u
(SCL only)
I
LI
1
In / Out leakage current, u
(SDA and SQW/OUT)
I
LO
1
Low level output voltage, V
V
OL
1)
V
= 4,5 V
0,4
Consumption current in the data transfer mode,
u
I
CCA
f
SCL
= 100 kHz
1500
Consumption current in the static mode, u
I
CCS
V
= 5 V and
SDA,
SCL = 5 V
200
Consumption current in the battery mode
(SQW/OUT OFF., 32 kHz ON), uA
I
BAT1
V
CC
= 0 V, V
BAT
= 3 V
0,5
Consumption current in the battery mode
(SQW/OUT ON, 32 kHz ON), uA
I
BAT2
V
CC
= 0 V, V
BAT
= 3 V
0,8
Low level voltage is determined under the load current of 5 m; V
OL
= GND under the capacitance load
Dynamic parameters of the microcircuit IN1307
(
= 40...+ 85
, V
CC
= 4,5 5,5 V )
Norm
Parameter Description,
Measurement Unit
Identification
Measurement
Mode
Not
less
Not more
Cycle frequency SCL, kHz
f
SCL
0 100
Time of the bus vacant status between the
statuses of STOP and START, usec
t
BUF
4,7
Hold time (repeated) of START status, usec
t
HD:STA
1)
4,0
Duration of the low status of the cycle pulse
SCL, usec
t
LOW
4,7
Duration of the cycle pulse high status SCL,
usec
t
HIGH
4,0
Pre-set time for the repeated status START,
usec
t
SU:STA
4,7
Data hold time, usec
t
HD:DAT
2)
0
Data pre-set time, nsec
t
SU:DAT
250
Rise time of signals SDA and SCL, nsec
t
R
1000
Drop time of signals SDA and SCL, nsec
t
F
300
Pre-set time for the status STOP, usec
t
SU:STO
4,7
TotaL capacitance load per each bus line, pF
C
B
400
IN / OUT capacitance, pF
C
I/O
10
10
Load capacitance of the quartz resonator, pF
LX
12,5
12,5
After this time interval the first time cycle signal is formed;
Device should internally ensure the hold time, at least, 300 nsec for the signal SDA (relative to V
IHMIN
of signal
SCL) in order to overlap the indeterminancy area of the fall signal of SCL.
maximum value t
HD:DAT
should be definite in that case, if the device does not increase duration of the low
status (t
LOW
) of signal SCL.
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TECHNICAL DATA
Timing Chart
IN1307 Functioning
IN1307 operates as the driven device on the serial bus. For access to it it is required to set the
status START and to send after the register address the device identification code. It is possible to
address the next register consequently, until the status STOP is set. When V
CC
drops below 1,25 x
V
BAT
, the access in progress to the device is ceased and the address counter is reset. At this time the
device does not recognize the input data, excluding the erroneous information writing. When V
CC
drops
below V
BAT
, the device switches over to the battery mode, consuming low power. When switching on
the power supply V
CC
above V
BAT
+ 0,2 V, the device switches over from the battery power supply to
V
CC
; and recognizes the input data, when V
CC
becomes above 1,25 x V
BAT
Addresses Chart of RTC and RAM
Addresses chart of the registers RTC and RAM is indicated in
the Figure. Hour registers of the real time are positioned at the
addresses 00h 07h. RAM registers are positioned at the
addresses of 08h 3Fh. In the mode of the multi-byte access,
when reaching by the pointer of the address 3Fh, the end of the
RAM address space, there happens transition to the register with
the address 00h, beginning of the hours area.
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TECHNICAL DATA
Hours and Calendar
Information on the time and date is obtained by means of reading the appropriate register bytes.
Hour registers of the real time are indicated in the Figure. Pre-setting and time and calendar
initialization are performed by means of writing the appropriate bytes. Information, contained in the
time and calendar registers, represents the binary-decimal code. Bit 7 of register 0 represents the hour
stop bit (CH). When this bit is set to "1" , the generator is off.
When switching on the power supply, the initial status of all registers is not determined. It is necessary
to enable the generator (bit CH = 0) when setting the initial configurations.
IN1307 operates in the 12-hour or in the 24-hour format. The bit 6 of the watch register determines the
operational mode. 12-hour mode corresponds to the high level. In the 12-hour mode the bit 5 is the
AM/PM bit. The high level corresponds to PM. In the 24-hour mode, the 5 is the second bit of tens of
hours (20 -23 hours).
During application of the signal "START" to the two-wire bus there happens transfer of the real
time to the auxiliary set of registers. The time data are read from these auxiliary registers, while the
watch proceeds in operation. This eliminates the necessity of repeated reading in case of updating the
basic registers in the access process.
Registers RTC IN1307
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TECHNICAL DATA
Control Register
Control register is used for control of pin SQW/OUT.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OUT
X X SQWE
X X RS1
RS0
OUT (output control) : This bit presets the output logic level of the pin SQW/OUT, when the output
of the rectangular signal is locked.
SQWE (rectangular signal enabling): This bit, pre-set to the logic "1", activates the generator
output. Frequency of the output rectangular signal is determined by the bits RS0 and RS1.
RS (frequency selection): These bits determine the frequency of the output rectangular signal, when
the output of the rectangular signal is activated. The table indicates the frequencies, which can be
selected by the bits RS.
RS1 RS0
Frequency
SQW/OUT
0 0 1
Hz
0 1 4,096
kHz
1 0 8,192
kHz
1 1 32,768
Two-wire Serial Data Bus
IN1307 supports the bi-directional two-wire bus and the protocol of the data exchange. The bus
can be controlled by the "master" device, which generates the cycle signal (SCL), controls access to
the bus, generates the statuses START and STOP. Typical configuration of the bus with the two-wire
protocol is indicated in Figure.
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TECHNICAL DATA
Data transfer can be initiated only when the bus is not occupied. In the process of the data
transfer the data line should remain stable, while the line of the cycle signal is in the high status.
Status alterations of the data line at that moment, when the cycle line is in the high status, will be
regarded as the control signals.
In compliance with this the following conditions are determined:
Bus not occupied: both the data line and the cycle signal are in the HIGH
Data transfer start: Status alteration of the data line during transition from HIGH to LOW, while the
cycle line is in the HIGH status, is determined as the status START.
Data transfer stop: Status alteration of the data line during transition from LOW to HIGH, while the
cycle line is in the HIGH status, is determined as the status STOP.
Valid data: Data line status complies with the valid data, when after the status START the data line is
stable during the HIGH status of the cycle signal. Data on the line should be altered at the time of the
LOW status of the cycle signal. One cycle pulse per one data bit.
Each data transfer starts at the beginning of the status START and ceases at the beginning of the
status STOP. Number of the data bytes, transferred between the statuses START and STOP is not
limited and is determined by the master device. Information is transferred byte by byte, and each
receipt is confirmed by the ninth byte. IN1307 operates in the normal mode only (100 kHz).
Confirmation of receipt: Each receiving device, when it being addressed, has to generate the recept
confirmation after receiving each byte. Master device should generate the cycle pulses, which are
allocated in compliance with the confirmation bits.
If the receipt confirmation signal is in the high status, then on arrival of the confirmation cycle pulse,
the device, confirming the receipt, should switch over the SDA line to the low status. Of course, there
should be considered the pre-set time and the hold time. The master device should signalize on
completion of the data transfer to the "slave" device, ceasing generation of the confirmation bit on
receiving the receipt confirmation from the "slave" cycle pulse. In this case, the slave one should
switch over the data line to the low status, in order to enable the master one generate the condition
of STOP.
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TECHNICAL DATA
Data Transfer by the Serial Two-wire Bus
Depending on the status of bit
W
R /
, there are possible two types of transfer:
1.Data are transferred from the master transmitter to the slave receiver. The first byte,
transmitted by the master one, is the address for the slave one. Then follows a sequence of the
data bytes. The slave one returns the receipt confirmation bytes after each received byte. Order of
the data transfer: the first is the most senior digit (MSB).
2. The data are transferred from the slave transmitter to the master receiver. The first byte
(address of slave) is applied to the master. Then the master returns the confirmation bit. This
follows after the transfer by the slave of the data sequence. The master returns the receipt
confirmation bit after each received byte, with the exception of the last byte. After receipt of the last
byte the receipt confirmation bit is not returned.
The master device generates all cycle pulses and the statuses START and STOP. Transfer is
completed at emergence of the status STOP or the repeated emergence of the status START. As the
repeated status START is the beginning of the next serial transfer, the bus is not vacated.The data
transfer order: the first is the most senior digit (MSB).
IN1307 can operate in the two following modes:
1.Mode of slave receiver (write mode of IN1307): Serial data and cycles are received via SDA
and SCL appropriately. After transfer of each byte the confirmation bit is sent. The statuses START
and STOP are recognized as the beginning and the end of the serial transfer. The address recognition
is performed by means of the hardware after receipt of the "slave" address and the direction bit. The
address byte isthe first byte, received after occurrence of the START status, generated by the
"master". The address byte contains the seven address bits of IN1307, equal to 1101000,
accompanied by the direction bit (
W
R /
), which for write is equal to 0.After receipt and decoding of
the address byte, DS1307 applies confirmation to the line SDA. After confirmation by IN1307 of the
"slave" address and the write bit, the master sends the register address of IN1307. Thus the register
indicator will be preset in IN1307. Then the smart shall start to send each data byte with the
subsequent receipt confirmation of each byte. Upon completion of writing the "master" shall formulate
the status STOP for termination of the data transfer.
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TECHNICAL DATA
Data writing mode of slave receiver
2. Mode of slave receiver (write mode from IN1307): The first byte is received and processed as
in the mode of the slave receiver. However, in this mode the direction bit will signify, that the
transmission direction is changed. IN1307 sends the serial data by SDA, the cycle pulses - by SCL.
statuses START and STOP are understood as the beginning and end of the consecutive transmission.
The address byte is the first byte, received after occurrence of the status START, generated by the
master. The address byte contains the seven bits of the address DS1307, equal to 1101000,
accompanied by the direction bit (
W
R /
), which is equal to 1 for reading. After receipt and decoding
of the address byte IN1307 receives confirmation from the line SDA. Then IN1307 starts to send the
data from the address, which is indicated by the register indicator. If the register indicator is not written
prior to initialization of the read mode, then the first read address is the last address , retained in the
register indicator. IN1307 should send the bit of non-confirmation, in order to complete the reading.
Data reading mode of slave transmitter
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TECHNICAL DATA
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