1
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEED BA C K
CLK_IN
O E/RST
P LL_EN
PLL
Q
0
Q
1
Q
2
Q
3
Q
4
0
1
/2
JULY 2000
2000 Integrated Device Technology, Inc.
DSC-5816/1
c
QS5935
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
5V operation
Five low noise CMOS level outputs
<500ps output skew, Q
0
Q
4
Outputs 3-state and reset while OE/RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Balanced drive outputs 36mA
80MHz maximum frequency
Available in QSOP package
DESCRIPTION
The QS5935 Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to a reference clock input. Five outputs are
available: Q
0
Q
4
. Careful layout and design ensure <500ps skew between
the Q
0
Q
4
. The QS5935 includes an internal RC filter which provides
excellent jitter characteristics and eliminates the need for external compo-
nents. The PLL can also be disabled by the PLL_EN signal to allow low
frequency or DC testing. The QS5935 is designed for use in cost sensitive
high-performance computing systems, workstations, multi-board comput-
ers, networking hardware, and mainframe systems. Several can be used
in parallel or scattered throughout a system for guaranteed low skew,
system-wide clock distribution networks. In the QSOP package, the QS5935
clock driver represents the best value in small form factor, high-performance
clock management products.
2
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
QSOP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
OE/RST
FEEDBACK
AV
DD
AGND
CLK_IN
V
DD
GND
Q
0
Q
4
N/C
GND
Q
3
Q
2
GND
PLL_EN
GND
Q
1
V
DD
V
DD
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Max.
Unit
AV
DD,
V
DD
Supply Voltage to Ground
0.5 to +7
V
DC Input Voltage V
IN
0.5 to V
DD
+0.5
V
Maximum Power Dissipation (T
A
= 85C)
0.5
W
T
STG
Storage Temperature Range
65 to +150
C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25
C, f = 1MHz, V
IN
= 0V) (1)
Pins
Typ.
Max.
Unit
C
IN
3
4
pF
C
OUT
4
5
pF
NOTE:
1. Capacitance is characterized but not tested.
PIN DESCRIPTION
Pin Name
I/O
Description
CLK_IN
I
Reference clock input
FEEDBACK
I
External feedback provides flexibility for different output frequency relationships
Q
0
-Q
4
O
Clock outputs
OE/RST
I
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,
outputs are enabled.
PLL_EN
I
When 1, PLL is enabled. When 0, PLL is disabled and the output for Q
0
-Q
4
will be CLK_IN/2 in frequency. This allows the
CLK_IN input to be single-stepped for system debug.
V
DD
--
Power supply for output buffers
AV
DD
--
Power supply for phase lock loop and other internal circuitries
GND
--
Ground supply for output buffers
AGND
--
Ground supply for phase lock loop and other internal circuitries
3
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
(1)
Min.
Typ.
Max.
Unit
t
SKR
Output Skew Between Rising Edges, Q
0
-Q
4
(2,3)
--
--
500
ps
t
SKF
Output Skew Between Falling Edges, Q
0
-Q
4
(2,3)
--
--
500
ps
t
PW
Pulse Width, Q
0
-Q
4
T
CYC
/2
- 0.4
--
T
CYC
/2 + 0.4
ns
t
J
Cycle-to-Cycle Jitter
(2,5)
- 0.15
--
+0.15
ns
t
PD
CLK_IN to Feedback Delay
(2,6)
- 500
--
+500
ps
t
LOCK
CLK_IN to Phase Lock
--
--
10
ms
t
PZH
t
PZL
Output Enable Time, OE/RST LOW to HIGH
(4)
0
--
14
ns
t
PHZ
t
PLZ
Output Disable Time, OE/RST HIGH to LOW
(2,4)
0
--
14
ns
t
R,
t
F
Output Rise/Fall Times, 0.2V
DD
0.8V
DD
(2)
--
--
2.5
ns
t
R,
t
F
Maximum Rise/Fall Times, 0.8V to 2V
--
--
3
ns
F
I
Input Clock Frequency
10
--
80
MHz
t
PWC
Input Clock Pulse, HIGH or LOW
(7)
2
--
--
ns
D
H
Duty Cycle, CLK_IN
(7)
25
--
75
%
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. This parameter is guaranteed by characterization but not tested.
3. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
4. Measured in open loop mode PLL_EN = 0.
5. Jitter is characterized using an oscilloscope, Q output at 20MHz. Measurement is taken one cycle after jitter.
6. t
PD
measured at device inputs at 1.5V, Q output at 80MHz.
7. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, AV
DD/
V
DD
= 5.0V 10%
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
--
--
0.8
V
V
OH
Output HIGH Voltage
I
OH
=
-36mA
V
DD
0.75
--
--
V
I
OH
=
-100A
V
DD
0.2
--
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 36mA
--
--
0.45
V
V
DD
= Min., I
OL
= 100
A
--
--
0.2
V
V
H
Input Hysteresis
--
--
100
--
mV
I
OZ
Output Leakage Current
V
OUT
= V
DD
or GND,
V
DD
= Max., Outputs Disabled
--
--
5
A
I
IN
Input Leakage Current
V
IN
= AV
DD
or GND, AV
DD
= Max.
--
--
5
A
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
I
DDQ
Quiescent Power Supply Current
V
DD
= Max., OE/RST = LOW,
CLK_IN = LOW, All outputs unloaded
--
1
mA
I
DD
Power Supply Current per Input HIGH
V
DD
= Max., V
IN
= 3.4V
0.7
1.5
mA
I
DDD
Dynamic Power Supply Current
(1)
V
DD
= Max., C
L
= 0pF
--
0.4
mA/MHz
NOTE:
1. This value is guaranteed but not tested.
4
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
30pF
300
7.0V
O UTP U T
V
D D
OUTP UT
1.0ns
1.0ns
2.0V
0.8V
3.0V
0 V
V
th
= 1 .5V
t
R
t
F
0 V
0.5V
D D
0.8V
D D
0.2V
D D
V
D D
t
P W
CONTROL
INPU T
EN A BL E
D ISA B LE
3 V
1.5V
0 V
3.5V
0V
0.5V
D D
OU TP UT
N OR MAL LY
LO W
O UTP UT
NO R M AL LY
HIGH
SW ITCH
O P EN
SW ITCH
C LO SED
t
P Z H
0.3V
0.3V
t
PZ L
t
P LZ
t
P H Z
0.5V
D D
V
O H
V
O L
100
100
AC TEST LOADS AND WAVEFORMS
TEST CIRCUIT 1
TTL INPUT TEST WAVEFORM
CMOS OUTPUT WAVEFORM
TEST CIRCUIT 2
ENABLE AND DISABLE TIMES
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timing parameters.
5
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
CLK_IN
t
P D
t
J
t
SK F
FE EDB AC K
Q
Q
0
-Q
4
AC TIMING DIAGRAM
NOTES:
1. AC Timing Diagram applies to Q output connected to FEEDBACK .
2. All parameters are measured at 0.5V
DD
except for t
PD
, which is measured at 1.5V
6
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
QS
X
Package
5935
Low Skew CMOS PLL Clock Driver
with Integrated Loop Filter
XXXX
Device Type
X
Process
Blank
Q
Quarter Size Outline Package
Industrial (-40C to +85C)
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
PDF 
ZIP