FEATURES:
128K x 8 CMOS static RAM
Equal access and cycle times
-- Commercial: 70ns
Two Chip Selects plus one Output Enable pin
Bidirectional inputs and outputs directly TTL-compatible
Low power consumption via chip deselect
Available in 300 and 400 mil Plastic SOJ packages
Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 1996
1996 Integrated Device Technology, Inc.
DSC-3568/-
CMOS STATIC RAM
1 MEG (128K x 8-BIT)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT71024S70
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT71024 is a 1,048,576-bit medium-speed static
RAM organized as 128K x 8. It is fabricated using IDT's high-
performance, high-reliability CMOS technology. This state-
of-the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.
The IDT71024 has an output enable pin which operates as
fast as 30ns, with address access times as fast as 70ns
available. All bidirectional inputs and outputs of the IDT71024
are TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used; no clocks or
refreshes are required for operation.
The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ
and 32-pin 400 mil Plastic SOJ packages.
1
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
A
0
A
16
3568 drw 01
8
8
I/O
0
I/O
7
8
CONTROL
LOGIC
WE
OE
CS1
CS2
2
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE
(1,2)
INPUTS
WE
WE
CS1
CS1
CS2
OE
OE
I/O
FUNCTION
X
H
X
X
High-Z
DeselectedStandby (I
SB
)
X
V
HC
(3)
X
X
High-Z
DeselectedStandby (I
SB1
)
X
X
L
X
High-Z
DeselectedStandby (I
SB
)
X
X
V
LC
(3)
X
High-Z
DeselectedStandby (I
SB1
)
H
L
H
H
High-Z
Outputs Disabled
H
L
H
L
DATA
OUT
Read Data
L
L
H
X
DATA
IN
Write Data
NOTES:
3568 tbl 01
1. H = V
IH
, L = V
IL
, X = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
-0.2V.
3. Other inputs
V
HC
or
V
LC.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Com'L.
Unit
V
TERM
(2)
Terminal Voltage with
0.5 to +7.0
V
Respect to GND
T
A
Operating Temperature
0 to +70
C
T
BIAS
Temperature Under Bias
55 to +125
C
T
STG
StorageTemperature
55 to +125
C
P
T
Power Dissipation
1.25
W
I
OUT
DC Output Current
50
mA
NOTES:
3568 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
PIN CONFIGURATION
SOJ
TOP VIEW
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz, SOJ package)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
8
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
8
pF
NOTE:
3568 tbl 03
1. This parameter is guaranteed by device characterization, but is not prod-
uction tested.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter Min. Typ. Max.
Unit
V
CC
Supply Voltage 4.5 5.0 5.5
V
GND
Supply Voltage 0 0 0
V
V
IH
Input High Voltage 2.2 -- Vcc+0.5
V
V
IL
Input Low Voltage 0.5
(1)
-- 0.8
V
NOTE:
3568 tbl 04
1. V
IL
(min.) = 1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
10%
IDT71024
Symbol
Parameter
Test Condition
Min. Max.
Unit
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
= GND to V
CC
-- 5
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS1
= V
IH
, CS2 = V
IL
, V
OUT
= GND to V
CC
-- 5
A
V
OL
Output LOW Voltage
I
OL
= 8mA, V
CC
= Min.
-- 0.4
V
V
OH
Output HIGH Voltage
I
OH
= 4mA, V
CC
= Min.
2.4 --
V
3568 tbl 05
.
5
6
7
8
9
10
11
12
NC
A
16
A
14
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
A
15
A
12
A
7
A
6
A
5
A
4
CS2
A
13
A
8
A
9
A
11
WE
A
10
3568 drw 02
A
3
13
20
OE
14
19
15
18
16
GND
17
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
CC
CS1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
S032-3
SO32-3
3
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5.0V
10%, V
LC
= 0.2V, V
HC
= V
CC
0.2V)
71024S70
Symbol
Parameter
Com'l. Mil.
Unit
I
CC
Dynamic Operating Current, CS2
V
IH
and
140
--
mA
CS2
V
IH
and
CS1
V
IL
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
I
SB
Standby Power Supply Current (TTL Level)
35
--
mA
CS1
V
IH
or CS2
V
IL
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
I
SB1
Full Standby Power Supply Current
10
--
mA
(CMOS Level)
CS1
V
HC,
or CS2
V
LC
Outputs Open,
V
CC
= Max., f = 0
(2)
, V
IN
V
LC
or V
IN
V
HC
NOTES:
3568 tbl 06
1.All values are maximum guaranteed values.
2.f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
Figure 1. AC Test Load
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
3568 tbl 07
3568 drw 04
480
255
5pF*
DATA
OUT
5V
3568 drw 03
480
255
30pF
DATA
OUT
5V
4
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
10%, Commercial Temperature Range)
71024S70
Symbol
Parameter
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
70
--
ns
t
AA
Address Access Time
--
70
ns
t
ACS
Chip Select Access Time
--
70
ns
t
CLZ
(2)
Chip Select to Output in Low-Z
3
--
ns
t
CHZ
(2)
Chip Deselect to Output in High-Z
0
30
ns
t
OE
Output Enable to Output Valid
--
30
ns
t
OLZ
(2)
Output Enable to Output in Low-Z
0
--
ns
t
OHZ
(2)
Output Disable to Output in High-Z
0
30
ns
t
OH
Output Hold from Address Change
4
--
ns
t
PU
(2)
Chip Select to Power-Up Time
0
--
ns
t
PD
(2)
Chip Deselect to Power-Down Time
--
70
ns
Write Cycle
t
WC
Write Cycle Time
70
--
ns
t
AW
Address Valid to End-of-Write
60
--
ns
t
CW
Chip Select to End-of-Write
60
--
ns
t
AS
Address Set-up Time
0
--
ns
t
WP
Write Pulse Width
45
--
ns
t
WR
Write Recovery Time
0
--
ns
t
DW
Data Valid to End-of-Write
30
--
ns
t
DH
Data Hold Time
0
--
ns
t
OW
(2)
Output Active from End-of-Write
5
--
ns
t
WHZ
(2)
Write Enable to Output in High-Z
0
30
ns
NOTES:
3568 tbl 08
1. 0
C to +70
C temperature range only.
2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
5
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS1
is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of
CS1
transition LOW and CS2 transition HIGH; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured
200mV from steady state.
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
ADDRESS
3568 drw 05
OE
CS1
(5)
(5)
(5)
(5)
CS2
DATA VALID
HIGH IMPEDANCE
AA
RC
OE
ACS
OLZ
CHZ
CLZ
(3)
OHZ
DATA
OUT
OUT
PU
PD
Vcc
SUPPLY
CURRENT
Icc
Isb
t
t
t
t
t
t
t
t
t
t
DATA
OUT
ADDRESS
3568 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
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