FUNCTIONAL BLOCK DIAGRAM - UTOPIA LEVEL 2 MODE
RxCLK
Clock/Data
Recovery
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Scrambler/
Descrambler
Tx/Rx ATM
Cell FIFO
Tx 0
Rx 0
Clock/Data
Recovery
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Scrambler/
Descrambler
Tx/Rx ATM
Cell FIFO
Tx 1
Rx 1
Clock/Data
Recovery
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Scrambler/
Descrambler
Tx/Rx ATM
Cell FIFO
Tx 2
Rx 2
PHY-ATM
Interface
(UTOPIA or DPI)
Microprocessor
(Utility Bus)
Interface
TxDATA[15:0]
TxCLK
RxDATA[15:0]
3
3
RxLED[2:0]
TxLED[2:0]
TxADDR[4:0]
RxADDR[4:0]
+
+
+
+
TxSOC
TxCLAV
TxPARITY
MODE[1:0]
RxSOC
RxCLAV
RxPARITY
4781 drw 01
+
+
ALE
AD[7:0]
OSC
Driver
Driver
Driver
Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
NOVEMBER 1998
1998 Integrated Device Technology, Inc.
DSC-4781/1
1
Triple Port PHY (Physical Layer)
for 25.6 and 51.2 Mbps
ATM Networks
PRELIMINARY
IDT77V1253
FEATURES
Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions for
three 25.6 Mbps ATM channels
Compliant to ATM Forum (af-phy-040.000) and ITU-T
I.432.5 specifications for 25.6 Mbps physical interface
Also operates at 51.2Mbps
UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
3-Cell Transmit & Receive FIFOs
LED Interface for status signalling
Supports UTP Category 3 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
144-pin PQFP Package (28 x 28 mm)
DESCRIPTION
The IDT77V1253 is a member of IDT's family of products
supporting Asynchronous Transfer Mode (ATM) data commu-
nications and networking. The IDT77V1253 implements the
physical layer for 25.6 Mbps ATM, connecting three serial
copper links (UTP Category 3) to one ATM layer device such
as a SAR or a switch ASIC. The IDT77V1253 also operates
at 51.2 Mbps, and is well suited to backplane driving applica-
tions.
The 77V1253-to-ATM layer interface is selectable as one
of three options: 16-bit UTOPIA Level 2, 8-bit UTOPIA Level
1 Multi-PHY, or triple 4-bit DPI (Data Path Interface).
The IDT77V1253 is fabricated using IDT's state-of-the-art
CMOS technology, providing the highest levels of integration,
performance and reliability, with the low-power consumption
characteristics of CMOS.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2
IDT77V1253
PRELIMINARY
25.6 and 51.2 Mbps ATM Triple PHY
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 1. Pin Assignments
VDD
GND
TX0-
TX0+
VDD
MM
MODE1
MODE0
GND
DNC
TXLED2
TXLED1
TXLED0
VDD
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXDATA8
TXDATA9
TXDATA10
TXDATA11
TXDATA12
TXDATA13
TXDATA14
TXDATA15
TXPARITY
TXSOC
TXADDR4
TXADDR3
VDD
TXADDR2
TXADDR1
TXADDR0
TXCLAV
TXCLK
GND
VDD
RXCLK
RXADDR0
RXADDR1
GND
RXADDR2
RXADDR3
RXADDR4
RXCLAV
RXSOC
GND
VDD
RXPARITY
RXDATA15
RXDATA14
RXDATA13
RXDATA12
RXDATA11
RXDATA10
RXDATA9
RXDATA8
GND
VDD
RXDATA7
RXDATA6
RXDATA5
RXDATA4
VDD
GND
DNC
DNC
VDD
DA
SE
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
VDD
ALE
GND
VDD
GND
DNC
RXLED2
RXLED1
RXLED0
VDD
GND
RXDATA0
RXDATA1
RXDATA2
RXDATA3
OSC
TX1+
TX1-
GND
AGND
AVDD
MB
MA
RX0+
RX0-
AVDD
AGND
AGND
AVDD
RX1+
RX1-
AVDD
AGND
AGND
AVDD
AGND
AVDD
AGND
AGND
AVDD
RX2+
RX2-
AVDD
AGND
AGND
AVDD
AVDD
AGND
GND
TX2+
TX2-
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
77V1253
144-PQFP
4781 drw 02
IDT77V1253
PRELIMINARY
25.6 and 51.2 Mbps ATM Triple PHY
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3
LINE SIDE SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
RX0+, -
139, 138
In
Port 0 positive and negative receive differential input pair
RX1+, -
133, 132
In
Port 1 positive and negative receive differential input pair
RX2+, -
121, 120
In
Port 2 positive and negative receive differential input pair
TX0+, -
4, 3
Out
Port 0 positive and negative transmit differential output pair
TX1+, -
144, 143
Out
Port 1 positive and negative transmit differential output pair
TX2+, -
110, 109
Out
Port 2 positive and negative transmit differential output pair
UTILITY BUS SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
AD[7:0]
101, 100, 99, 98
In/Out
Utility bus address/data bus. The address input is sampled on
96, 95, 94, 93
the falling edge of ALE. Data is output on this bus when a
read is performed. Input data is sampled at the completion of
a write operation.
ALE
91
In
Utility bus address latch enable. Asynchronous input. An
address on the AD bus is sampled on the falling edge of ALE.
ALE may be either high low when the AD bus is being used
for data.
CS
90
In
Utility bus asynchronous chip select.
CS
must be asserted to
read or write an internal register. It may remain asserted at all
times if desired.
RD
89
In
Utility bus read enable. Active low asynchronous input. After
latching an address, a read is performed by deasserting
WR
and
asserting
RD
and
CS
.
WR
88
In
Utility bus write enable. Active low asynchronous input. After
latching an address, a write is performed by deasserting
RD
, placing
data on the AD bus, and asserting
WR
and
CS
. Data is sampled
when
WR
or
CS
is deasserted.
MISCELLANEOUS SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
DA
103
In
Reserved signal. This input must be connected to logic low.
DNC
12, 82, 105, 106
Out
Do Not Connect. Do not connect these pins to anything external
to the chip. They must remain open.
INT
85
Out
Interrupt.
INT
is an open-drain output, driven low to indicate an
open drain
interrupt. Once low,
INT
remains low until the interrupt status in the
appropriate Interrupt Status Register is read. Interrupt sources
are programmable via the Interrupt Mask Registers.
MA
114
In
Reserved signal. This input must be connected to logic low.
MB
115
In
Reserved signal. This input must be connected to logic low.
MM
6
In
Reserved signal. This input must be connected to logic high.
MODE[1:0]
7, 8
In
Mode Selects. They determine the configuration of the PHY/ATM
interface. 00 = UTOPIA Level 2. 01 = UTOPIA Level 1. 10 = DPI.
11 is reserved.
OSC
126
In
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz
for 25.6 Mbps; 64 MHz for 51.2 Mbps.
RST
87
In
Reset. Active low asynchronous input resets all control logic,
counters and FIFOs. A reset must be performed after power up prior
to normal operation of the part.
RXLED[2:0]
81, 80, 79
Out
Receive LED drivers. Driven low for 2
23
RCLK or DPICLK cycles,
beginning with RXSOC when that port receives a good (non-null and
non-errored) cell. Drives 8 mA both high and low. One per port.
TABLE 1. SIGNAL DESCRIPTIONS
4
IDT77V1253
PRELIMINARY
25.6 and 51.2 Mbps ATM Triple PHY
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RXREF
9
Out
Receive Reference. Active low, synchronous to OSC.
RXREF
pulses low for a programmable number of clock cycles when an X_8
command byte is received. Register 0x40 is programmed to indicate
which port is referenced.
SE
102
In
Reserved signal. This input must be connected to logic low.
TXLED[2:0]
13, 14, 15
Out
Ports 2 thru 0 Transmit LED driver. Goes low for 2
23
TCLK or
DPICLK cycles, beginning with TXSOC when this port receives a cell
for transmission. 8mA drive current both high and low. One per port.
TXREF
10
In
Transmit Reference. Synchronous to OSC. When this pin is
asserted, an X_8 command byte is inserted into the transmit data
stream. Logic for this signal is programmed in register 0x40.
Typical application is WAN timing.
POWER SUPPLY SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
AGND
112, 117, 118,
-
Analog ground. AGND supply a ground reference to the analog
123,124,127,
portion of the chip, which sources a more constant current
129,130,135,
than the digital portion.
136, 141
AVDD
113, 116, 119,
-
Analog power supply. 3.3
0.3V AVDD supply power to the
122, 125, 128,
analog portion of the chip, which draws a more constant
131, 134, 137,
current than the digital portion.
140
GND
2, 11, 44, 50, 56
-
Digital Ground
67, 77, 83, 86,
97, 107, 111, 142
VDD
1, 5, 16, 38, 45
-
Digital power supply. 3.3
0.3V
57, 68, 78, 84,
92, 104, 108
16-BIT UTOPIA 2 SIGNALS (MODE[1:0] = 00)
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
RXADDR[4:0]
53, 52, 51, 49, 48
In
Utopia 2 Receive Address Bus. This bus is used in polling and
selecting the receive port. The port addresses are defined in bits
[4:0] of the Enhanced Control Registers.
RXCLAV
54
Out
Utopia 2 Receive Cell Available. Indicates the cell available status
of the addressed port. It is asserted when a full cell is available for
retrieval from the receive FIFO. When none of the three ports is
addressed, RXCLAV is high impedance.
RXCLK
46
In
Utopia 2 Receive Clock. This is a free running clock input.
RXDATA[15:0]
59, 60, 61, 62,
Out
Utopia 2 Receive Data. When one of the three ports is selected, the
63, 64, 65, 66,
77V1253 transfers received cells to an ATM device across this bus.
69, 70, 71, 72,
Also see RXPARITY.
73, 74, 75, 76
RXEN
47
In
Utopia 2 Receive Enable. Driven by an ATM device to indicate its
ability to receive data across the RXDATA bus.
RXPARITY
58
Out
Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0].
RXSOC
55
Out
Utopia 2 Receive Start of Cell. Asserted coincident with the first
word of data for each cell on RXDATA.
TXADDR[4:0]
36, 37, 39, 40, 41
In
Utopia 2 Transmit Address Bus. This bus is used in polling and
selecting the transmit port. The port addresses are defined in bits
[4:0] of the Enhanced Control Registers.
TXCLAV
42
Out
Utopia 2 Transmit Cell Available. Indicates the availability of room in
the transmit FIFO of the addressed port for a full cell. When none of
the three ports is addressed, TXCLAV is high impedance.
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
TABLE 1. SIGNAL DESCRIPTIONS (continued)
IDT77V1253
PRELIMINARY
25.6 and 51.2 Mbps ATM Triple PHY
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
5
TXCLK
43
In
Utopia 2 Transmit Clock. This is a free running clock input.
TXDATA[15:0]
32, 31, 30, 29,
In
Utopia 2 Transmit Data. An ATM device transfers cells across this
28, 27, 26, 25,
bus to the 77V1253 for transmission. Also see TXPARITY.
24, 23, 22, 21,
20, 19, 18, 17
TXEN
34
In
Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is
transmitting data across the TXDATA bus.
TXPARITY
33
In
Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0].
Parity is checked and errors are indicated in the Interrupt Status
Registers, as enabled in the Master Control Registers. No other
action is taken in the event of an error. Tie high or low if unused.
TXSOC
35
In
Utopia 2 Transmit Start of Cell. Asserted coincident with the first
word of data for each cell on TXDATA.
8-BIT UTOPIA LEVEL 1 SIGNALS (MODE[1:0] = 01)
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
RXCLAV[2:0]
65, 66, 54
Out
Utopia 1 Receive Cell Available. Indicates the cell available status
of the respective port. It is asserted when a full cell is available for
retrieval from the receive FIFO.
RXCLK
46
In
Utopia 1 Receive Clock. This is a free running clock input.
RXDATA[7:0]
69, 70, 71, 72,
Out
Utopia 1 Receive Data. When one of the three ports is selected, the
73, 74, 75, 76
77V1253 transfers received cells to an ATM device across this bus.
Bit 5 in the Diagnostic Control Registers determines whether
RXDATA tri-states when
RXEN
[2:0] are high. Also see RXPARITY.
RXEN
[2:0]
49, 48, 47
In
Utopia 1 Receive Enable. Driven by an ATM device to indicate its
ability to receive data across the RXDATA bus. One for each port.
RXPARITY
58
Out
Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0].
RXSOC
55
Out
Utopia 1 Receive Start of Cell. Asserted coincident with the first
word of data for each cell on RXDATA. Tri-statable as determined
by bit 5 in the Diagnostic Control Registers.
TXCLAV[2:0]
40, 41, 42
Out
Utopia 1 Transmit Cell Available. Indicates the availability of room in
the transmit FIFO of the respective port for a full cell.
TXCLK
43
In
Utopia 1 Transmit Clock. This is a free running clock input.
TXDATA[7:0]
24, 23, 22, 21,
In
Utopia 1 Transmit Data. An ATM device transfers cells across this
20, 19, 18, 17
bus to the 77V1253 for transmission. Also see TXPARITY.
TXEN
[2:0]
26, 25, 34
In
Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is
transmitting data across the TXDATA bus. One for each port.
TXPARITY
33
In
Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0].
Parity is checked and errors are indicated in the Interrupt Status
Registers, as enabled in the Master Control Registers. No other
action is taken in the event of an error. Tie high or low if unused.
TXSOC
35
In
Utopia 1 Transmit Start of Cell. Asserted coincident with the first
word of data for each cell on TXDATA.
DPI MODE SIGNALS (MODE[1:0] = 10)
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
DPICLK
43
In
DPI Source Clock for Transmit. This is the free-running clock used
as the source to generate Pn_TCLK.
Pn_RCLK
51, 49, 48
In
DPI Port 'n' Receive CLock. Pn_RCLK is cycled to indicate that
the interfacing device is ready to receive a nibble of data on
Pn_RD[3:0] of port 'n'.
Pn_RD[3:0]
63, 64, 65, 66,
Out
DPI Port 'n' Receive Data. Cells received on port 'n' are passed to
69, 70, 71, 72,
the interfacing device across this bus. Each port has its own
73, 74, 75, 76
dedicated bus.
TABLE 1. SIGNAL DESCRIPTIONS (continued)
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
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