1
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
MARCH 2001
IDT74FCT88915TT
55/70/100/133
COMMERCIAL TEMPERATURE RANGE
LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
DESCRIPTION:
The FCT88915TT uses phase-lock loop technology to lock the frequency
and phase of outputs to the input reference clock. It provides low skew clock
distribution for high performance PCs and workstations. One of the outputs is
fed back to the PLL at the FEEDBACK input resulting in essentially zero delay
across the device. The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The VCO is designed to run optimally between
20MHz and f2Q Max.
The FCT88915TT provides eight outputs with 500ps skew. The Q5 output is
inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs
at half the Q frequency.
The FREQ_SEL control provides an additional 2 option in the output path.
PLL _EN allows bypassing of the PLL, which is useful in static test modes. When
PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the
input frequency is not limited to the specified range and the polarity of outputs
is complementary to that in normal operation (PLL_EN = 1). The LOCK output
attains logic high when the PLL is in steady-state phase and frequency lock.
The FCT88915TT requires external loop filter components as recom-
mended in Figure 2.
Phase/Freq.
Detector
M
u
x
0
1
SYNC (0)
FEEDBAC K
SYNC (1)
REF_SEL
PLL_EN
M ux
0
1
Divide
-By-2
(
1)
(
2)
1
0
M
u
x
C harge Pum p
Voltage
Controlled
O scilator
RST
FREQ _SEL
2Q
Q 0
Q 1
Q 2
Q 3
Q 4
Q 5
Q /2
D
Q
C P
Q
R
D
Q
C P
Q
R
D
Q
C P
R
D
Q
C P
R
D
Q
C P
R
D
Q
C P
R
D
Q
C P
R
D
Q
CP
LF
LO CK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2001 Integrated Device Technology, Inc.
DSC-4245/2
FEATURES:
0.5 MICRON CMOS Technology
Input frequency range: 10MHz f2Q Max. spec
(FREQ_SEL = HIGH)
Max. output frequency: 133MHz
Pin and function compatible with MC88915
Five non-inverting outputs, one inverting output, one 2x
output, one 2 output; all outputs are TTL-compatible
Output Skew < 500ps (max.)
Duty cycle distortion < 500ps (max.)
Part-to-part skew: 0.55ns (from t
PD
max. spec)
64/15mA drive at TTL output voltage levels
Available in PLCC and SSOP packages
FUNCTIONAL BLOCK DIAGRAM
2
COMMERCIAL TEMPERATURE RANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
R
S
T
V
C
C
Q
5
G
N
D
Q
4
V
C
C
2
Q
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
P
L
L
_
E
N
G
N
D
Q
1
V
C
C
Q
0
G
N
D
F
R
E
Q
_
S
E
L
FEEDBK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
SYNC(1)
28
4
3
2
1
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5
6
7
8
9
10
V
CC
RST
FEEDBACK
1
2
3
4
20
19
18
17
16
15
14
13
Q4
12
11
GND
Q/2
REF_SEL
SYNC(0)
V
CC
(AN)
LF
V
CC
GND
Q3
V
CC
Q2
GND
GND(AN)
LOCK
Q5
2Q
21
22
23
24
SYNC(1)
FREQ_SEL
GND
Q0
V
CC
Q1
GND
PLL_EN
25
26
27
28
SSOP
TOP VIEW
PLCC
TOP VIEW
PIN CONFIGURATIONS
Pin Name
I/O
Description
SYNC(0)
I
Reference clock input
SYNC(1)
I
Reference clock input
REF_SEL
I
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
FREQ_SEL
I
Selects between 1 and 2 frequency options (refer to functional block diagram)
FEEDBACK
I
Feedback input to phase detector
LF
I
Input for external loop filter connection
Q0-Q4
O
Clock outputs
Q5
O
Inverted clock output
2Q
O
Clock output (2 x Q frequency)
Q/2
O
Clock output (Q frequency 2)
LOCK
O
Indicates phase lock has been achieved (HIGH when locked)
RST
I
Asynchronous reset (active LOW)
PLL_EN
I
Disables phase-lock for low frequency testing (refer to functional block diagram)
PIN DESCRIPTION
3
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals.
3. Outputs and I/O terminals.
ABSOLUTE MAXIMUM RATINGS
(1)
(1)
(1)
(1)
(1)
Symbol
Description
Max.
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to 7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
A
Operating Temperature
0 to +70
C
T
BIAS
Temperature Under Bias
55 to +125
C
T
STG
StorageTemperature
55 to +125
C
I
OUT
DC Output Current
60 to 120
mA
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
4.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8
pF
CAPACITANCE
(T
A
= +25C, f = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
Symbol
Parameter
Min.
Max.
Unit
T
RISE/FALL
Rise/Fall Times, SYNC inputs
--
3
ns
(0.8V to 2.0V)
Frequency
Input Frequency, SYNC Inputs
10
2Q fmax
MHz
Duty Cycle
Input Duty Cycle, SYNC Inputs
25%
75%
--
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
V
CC
= Max.
V
I
= V
CC
--
--
1
A
I
IL
Input LOW Current
V
I
= GND
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
V
IH
Input Hysteresis
--
--
100
--
mV
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 15mA
2.4
3.5
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 64mA
--
0.2
0.55
V
I
CCL
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
2
4
mA
I
CCH
(Test mode, LF connected to GND)
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0C to 70C, V
CC
= 5.0V 5%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4
COMMERCIAL TEMPERATURE RANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
Symbol Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
1.5
mA
TTL Inputs HIGH
V
IN
= V
CC
2.1V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
= V
CC
--
0.5
0.7
mA/
Current
(4)
All Outputs Open
V
IN
= GND
MHz
C
PD
Power Dissipation Capacitance
50% Duty Cycle
--
25
40
pF
I
C
Total Power Supply Current
(5,6)
V
CC
= Max.
--
65
80
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50pF.
All other outputs open.
V
CC
= Max.
--
--
--
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50
Thevenin termination. All other outputs open.
P
D1
Power Dissipation
50
Thevenin termination @ 33MHz
--
120
--
mW
P
D2
Power Dissipation
50
Paralell termination to GND @ 33MHz
--
300
--
mW
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency
I
LOAD
= Dynamic Current due to load.
Max.
(2)
Symbol
Parameter
Min.
55
70
100
133
Unit
f2Q
Operating frequency 2Q Output
40
55
70
100
133
MHz
fQ
Operating frequency Q0-Q4, Q5 Outputs
20
27.5
35
50
66.7
MHz
fQ/2
Operating frequency Q/2 Output
10
13.75
17.5
25
33.3
MHz
NOTES:
1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded with 50pF.
OUTPUT FREQUENCY SPECIFICATIONS
5
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
Symbol
Parameter
Condition
(1)
Min.
Max.
Unit
t
RISE/FALL
Rise/Fall Time
C
L
= 50pF
1
(2)
2.5
ns
All Outputs
(between 0.2 V
CC
and 0.8 V
CC
)
R
L
= 500
t
RISE/FALL
Rise/Fall Time
C
L
= 20pF &
0.5
(2)
1.6
ns
2Q Output
(3)
(between 0.8V and 2.0V)
termination
(7)
t
PULSE WIDTH
Output Pulse Width
C
L
= 50pF
0.5t
CYCLE
0.5
(5)
0.5t
CYCLE
+ 0.5
(5)
ns
Q, Q, Q/2 Outputs
(3)
Q0-Q4, Q5, Q/2 @ V
CC
/2
t
PULSE WIDTH
Output Pulse Width
C
L
= 50pF
0.5t
CYCLE
1
(5)
0.5t
CYCLE
+ 1
(5)
ns
2Q Output
(3)
2Q Output @ V
CC
/2
t
PULSE WIDTH
Output Pulse Width
Termination as in
0.5t
CYCLE
0.5
(5)
0.5t
CYCLE
+ 0.5
(5)
ns
2Q Output
(3)
2Q @ 1.5V
note 7
t
PD
SYNC input to FEEDBACK delay
Load = 50
to V
CC
/2,
0.5
+0.5
ns
SYNC-FEEDBACK
(3)
(measured at SYNC0 or 1 and FEEDBACK
C
L
= 20pF
input pins)
0.1MF from LF to Analog GND
(9)
t
SKEWr
Output to Output Skew between outputs 2Q,
C
L
= 50pF
--
500
ps
(rising)
(3, 4)
Q0-Q4,Q/2 (rising edges only)
t
SKEWf
Output to Output Skew between outputs 2Q,
--
500
ps
(falling)
(3, 4)
Q0-Q4 (falling edges only)
t
SKEW
ALL
(3, 4)
Output to Output Skew
--
500
ps
2Q, Q/2, Q0-Q4 rising, Q5 falling
t
LOCK(6)
Time required to acquire Phase-Lock from time
1
(2)
10
ms
SYNC input signal is received
t
RST
Propagation Delay, RST (HIGH-to-LOW) to any
1.5
(2)
8
ns
Reset Q
Output (HIGH-to-LOW)
t
REC(10)
Reset Recovery Time
9
--
ns
Rising RST edge to falling SYNC edge
t
W(10)
Minimum Pulse Width RST input LOW
5
--
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, C
L
= 50pF (2pF), and at a fixed temperature and voltage.
5. t
CYCLE
= 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With V
CC
fully powered-on and an output properly connected to the FEEDBACK pin. t
LOCK
Max. is with C1 = 0.1F, t
LOCK
Min. is with C1 = 0.01F (where C1 is loop filter
capacitor shown in Figure 2).
7. These two specs ( t
RISE/FALL
and t
PULSE WIDTH
2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification. For these two specs to be guaranteed
by IDT, the termination scheme shown in Figure 1 must be used:
Rp
Zo (clock trace)
Rp = 1.5 Zo
Rs = Zo - 7
68040
P-Clock
Input
88915TT
2Q
Output
Rs
Figure 1. MC68040 P-Clock Input Termination Scheme
6
COMMERCIAL TEMPERATURE RANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
GENERAL AC SPECIFICATION NOTES, CONTINUED
8. The wiring diagrams and written explanations of Figures 4a-4c demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also, it is possible to feed back the Q5 output, thus creating a 180 phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
frequency range for each possible configuration:
9. The t
PD
spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input varies with process, temperature, and voltage. The phase
measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100
to V
CC
and 100
to ground. t
PD
measurements were made with the loop
filter connection shown in Figure 2 below:
Figure 2. Loop Filter Connection
External Loop
Filter
0.1F
C1
LF
Analog G N D
Phase Relationship
FREQ_SEL
Feedback
Allowable SYNC Input
Corresponding 2Q Output
of the Q Outputs
Level
Output
Frequency Range (MHz)
Frequency Range
to Rising SYNC Edge
HIGH
Q/2
10 to (2Q f
MAX
Spec)/4
40 to (2Q f
MAX
Spec)
0
HIGH
Any Q (Q0-Q4)
20 to (2Q f
MAX
Spec)/2
40 to (2Q f
MAX
Spec)
0
HIGH
Q5
20 to (2Q f
MAX
Spec)/2
40 to (2Q f
MAX
Spec)
180
HIGH
2Q
40 to (2Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
0
LOW
Q/2
5 to (2Q f
MAX
Spec)/8
20 to (2Q f
MAX
Spec)/2
0
LOW
Any Q (Q0-Q4)
10 to (2Q f
MAX
Spec)/4
20 to (2Q f
MAX
Spec)/2
0
LOW
Q5
10 to (2Q f
MAX
Spec)/4
20 to (2Q f
MAX
Spec)/2
180
LOW
2Q
20 to (2Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
0
7
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
Figure 3. Recommended Loop Filter and Analog Isloation Scheme for the FCT88915TT
NOTES:
1. Figure 3 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free
operation:
a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable
voltage transients at the LF pin.
b. The 10F low frequency bypass capacitor and the 0.1F high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88915TT's sensitivity to voltage
transients from the system digital V
CC
supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital V
CC
and ground noise, V
CC
step deviations should not occur at the 88915TT's
digital V
CC
supply. The purpose of the bypass filtering scheme shown in Figure 3 is to give the 88915TT additional protection from the power supply and ground plane transients
that can occur in a high frequency, high speed digital system.
c. The loop filter capacitor (0.1F) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
2. In addition to the bypass capacitors used in the analog filter of Figure 3, there should be a 0.1F bypass capacitor between each of the other (digital) four V
CC
pins and the board
ground plane. This will reduce output switching noise caused by the 88915TT outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass
capacitors should also be tied as close to the 88915TT package as possible.
Analog loop filter/VCO
section of the FCT88915TT
ANALOG V
CC
ANALOG G ND
LF
BOARD GND
BOARD V
C C
0.1
F (Loop
Filter Cap)
0.1
F
High
Freq.
Bypass
10
F
Low
Freq.
Bypass
A separate Analog power supply is not necessary
and should not be used. Following these pre-
scribed guidelines is all that is necessary to use
the FCT88915TT in a norm al digital environment.
8
COMMERCIAL TEMPERATURE RANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the Q/2 output is connected to the FEEDBACK input. The
internal PLL will line up the positive edges of Q/2 and SYNC. Thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2
frequency.
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1,
Q2, Q3 and Q4).
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the 2Q output is connected to the FEEDBACK input. The
internal PLL will line up the positive edges of 2Q and SYNC. Thus the 2Q
frequency will equal the SYNC frequency. The Q/2 output will always run at
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Figure 4c. Wiring Diagram and Frequency Relationships
with 2Q Output Feedback
Allowable Input Frequency Range:
10MHz to (f2Q F
MAX
Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q F
MAX
Spec)/8 (for FREQ_SEL LOW)
Figure 4a. Wiring Diagram and Frequency Relationships
with Q/2 Output Feedback
Allowable Input Frequency Range:
20MHz to (f2Q F
MAX
Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q F
MAX
Spec)/4 (for FREQ_SEL LOW)
Figure 4b. Wiring Diagram and Frequency Relationships
with Q4 Output Feedback
Allowable Input Frequency Range:
40MHz to (f2Q F
MAX
Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q F
MAX
Spec)/2 (for FREQ_SEL LOW)
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
In this application, the Q4 output is connected to the FEEDBACK input. The
internal PLL will line up the positive edges of Q4 and SYNC. Thus the Q4
frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The
Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run
at 2X the Q frequency.
Q/2
Q3
Q 2
PLL_EN
Q1
Q0
FQ_SEL
FEED BACK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
Q4
Q 5
2Q
LO W
50 MHz signal
12.5 M Hz feedback signal
HIG H
HIGH
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 M Hz
input
RST
FCT88915TT
Q /2
Q 3
Q 2
PLL_EN
Q 1
Q 0
FQ _SEL
FEEDBAC K
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
Q4
Q 5
2Q
FCT88915TT
LOW
50 M Hz signal
25 M Hz feedback signal
HIGH
HIGH
H IGH
25 M Hz
"Q"
Clock
O utputs
25 M Hz
input
12.5 M Hz
signal
RST
Q /2
Q 3
Q2
PLL_EN
Q1
Q0
FQ _SEL
FEED BAC K
REF_SEL
SYN C(0)
V
CC
(AN)
LF
GN D(AN)
Q4
Q5
2Q
FCT88915TT
LO W
50 MH z feedback signal
HIG H
HIG H
HIGH
25 MH z
"Q"
Clock
O utputs
50 M Hz
input
12.5 M Hz
input
RST
9
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
When the PLL_EN pin is LOW, the PLL is bypassed and the FCT88915TT
is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q
output is inverted from the selected SYNC input, and the Q outputs are divide-
by-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divide-
by-4 (negative edge triggered). With FREQ_SEL LOW the 2Q output is divide-
by-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A recommended test
configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie
PLL_EN and REF_SEL together and connect them to the test select logic.
This functionality is needed since most board-level testers run at 1 MHz or
below, and the FCT88915TT cannot lock onto that low of an input frequency.
In the test mode described above, any test frequency test can be used.
Figure 5. Multiprocessing Application Using the FCT88915 for Frequency Multiplication
and Low Board-to-Board skew
CM M U
CM M U
CPU
CM M U
CM M U
CM M U
CM M U
CM M U
CPU
CM M U
CM M U
CM M U
PLL
2f
PLL
2f
CPU
C ARD
CPU
C ARD
SYSTEM
CLOC K
SOU R CE
FCT88915TT
FCT88915TT
DISTRIBU TE
CLOCK @ f
C LOCK @ 2f
at point of use
ME MO RY
CONTROL
PLL
2f
ME MO RY
CAR DS
FCT88915TT
CLOCK
@ f
CLOC K @ 2f
at point of use
FCT88915 SYSTEM LEVEL TESTING FUNCTIONALITY
10
COMMERCIAL TEMPERATURE RANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
Propagation Delay, Output Skew
Test Circuits For All Outputs
Pulse
G enerator
R
T
D.U.T.
V
C C
V
IN
V
OU T
500
50pF
C
L
t
PD
SYNC IN PUT
(SYNC (1) or
SYNC (0))
FEED BACK
INPUT
Q/2 OUTPUT
Q0-Q4
OUTPUTS
Q5 OUTPUT
2Q O UTPUT
t
SK EW A LL
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
t
C YC LE SYN C IN PU T
t
SKEW f
t
SKEW r
t
SKE W f
t
C YC LE "Q " O U TP UTS
t
SKE W r
NOTES:
1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input. Therefore, the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the V
CC
/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as deviation around a center point.
3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice
the SYNC frequency, and the Q/2 output would run at half the SYNC frequency.
(These waveforms represent the configuration shown in Figure 4a)
11
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device Type
X
Package
J
PY
88915TT
PLCC
SSOP
Low Skew PLL-Based CMOS Clock Driver
74
0
C to +70C
FCT
X
Speed
55
70
100
133
55MHz Max. frequency
70MHz Max. frequency
100MHz Max. frequency
133MHz Max. frequency
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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