1
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
APRIL 2001
2001 Integrated Device Technology, Inc.
DSC-4646/1
c
IDT74FCT810BT/CT
COMMERCIAL TEMPERATURE RANGE
FAST CMOS
BUFFER/CLOCK DRIVER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
0.5 MICRON CMOS Technology
Guaranteed low skew < 600ps (max.)
Very low duty cycle distortion < 700ps (max.)
Low CMOS levels
TTL compatible inputs and outputs
TTL level output voltage swings
High drive: -32mA I
OH
, +48mA I
OL
Two independent output banks with 3-state control:
One 1:5 inverting bank
One 1:5 non-inverting bank
Available in QSOP, SSOP, and SOIC packages
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
PIN CONFIGURATION
QSOP/ SOIC/ SSOP
TOP VIEW
DESCRIPTION:
The 74FCT810T is a dual bank inverting/ non-inverting clock driver
built using advanced dual metal CMOS technology. It consists of two banks
of drivers, one inverting and one non-inverting. Each bank drives five output
buffers from a standard TTL-compatible input. The FCT810T has low output
skew, pulse skew and package skew. Inputs are designed with hysteresis
circuitry for improved noise immunity. The outputs are designed with TTL
output levels and controlled edge rates to reduce signal noise. The part has
multiple grounds, minimizing the effects of ground inductance.
O E
A
IN
A
O A
1
-O A
5
5
O E
B
IN
B
O B
1
-O B
5
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OA
1
OA
3
GND
OA
4
OA
5
OA
2
OE
A
IN
A
V
CC
GND
OB
1
OB
2
OB
3
GND
OB
4
GND
IN
B
OB
5
OE
B
V
CC
2
COMMERCIAL TEMPERATURE RANGE
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Names
Description
OE
A
, OE
B
3-State Output-Enable Inputs (Active LOW)
IN
A
, IN
B
Clock Inputs
OAx, OBx
Clock Outputs
CAPACITANCE (T
A
= +25
O
C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
4.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8
pF
NOTE:
1. This parameter is measured at characterization but not tested.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0C to +70C, V
CC
= 5V 5%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level (Input pins)
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current (Input pins)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
IL
Input LOW Current (Input pins)
V
CC
= Max.
V
I
= 0.5V
--
--
1
A
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
V
O
= 0.5V
--
--
1
I
I
Input HIGH Current
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
225
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 15mA
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
I
OH
= 32mA
(4)
2
3
--
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 48mA
--
0.3
0.55
V
V
IN
= V
IH
or V
IL
I
OFF
Input/Output Power Off Leakage
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
V
H
Input Hysteresis for all inputs
--
--
150
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
5
500
A
I
CCH
I
CCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition should not exceed one second.
3
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
C
formula. These limits are guaranteed but not tested.
6.
I
C
= I
QUIESCENT
+
I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
I
N
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
N
O
= Number of Outputs at f
O
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.
V
IN
= V
CC
--
60
100
A/MHz
Outputs Open
V
IN
= GND
OE
A
= OE
B
= GND
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
7.5
13
mA
Outputs Open
V
IN
= GND
f
O
= 25MHz
50% Duty Cycle
V
IN
= 3.4V
--
7.8
14
OE
A
= GND, OE
B
= V
CC
V
IN
= GND
V
CC
= Max.
V
IN
= V
CC
--
30
50.5
(5)
Outputs Open
V
IN
= GND
f
O
= 50MHz
50% Duty Cycle
V
IN
= 3.4V
--
30.5
52.5
(5)
OE
A
= OE
B
= GND
V
IN
= GND
4
COMMERCIAL TEMPERATURE RANGE
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH
, t
PHL
, t
SK
(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
CC
, operating temperature and process parameters. These propagation delay limits do not imply skew.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
FCT810BT
FCT810CT
Symbol
Parameter
Conditions
(1)
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
4.5
1.5
4.3
ns
t
PHL
IN
A
to OAx, IN
A
to OBx
R
L
= 500
t
R
Output Rise Time
--
1.5
--
1.5
ns
t
F
Output Fall Time
--
1.5
--
1.5
ns
t
SK1(O)
Output skew (same bank): skew between outputs of
--
0.5
--
0.3
ns
same bank and same package (same transition)
t
SK2(O)
Output skew (all banks): skew between outputs of
--
0.7
--
0.6
ns
all banks of same package (inputs tied together)
t
SK(P)
Pulse skew: skew between opposite transitions
--
0.7
--
0.7
ns
of same output (|t
PHL -
t
PLH
|)
t
SK(T)
Package skew: skew between outputs of different
--
1.2
--
1
ns
packages at same power supply voltage,
temperature, package type and speed grade
t
PZL
Output Enable Time
1.5
6
1.5
5
ns
t
PZH
OE
A
to OAx, OE
B
to OBx
t
PLZ
Output Disable Time
1.5
6
1.5
5
ns
t
PHZ
OE
A
to OAx, OE
B
to OBx
5
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
t
PLH1
O UTPUT 1
O UTPUT 2
t
SK (o)
t
PL H2
3V
0V
V
OH
1.5V
1.5V
V
O L
V
OH
1.5V
V
O L
INPUT
t
P HL1
t
PH L2
t
S K(o)
t
S K(o)
=
|t
PLH2 -
t
P LH1
|
or
|t
P HL2 -
t
PHL 1
|
C ONTRO L
INPUT
O UTPUT
NOR MA LLY
LOW
O UTPUT
NOR MA LLY
HIGH
3V
1.5V
0V
3.5V
0V
SW ITCH
CLO SE D
SW ITCH
O PEN
V
O L
V
O H
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
3V
0V
V
OH
t
P LH
t
PH L
V
OL
1.5V
1.5V
t
R
t
F
2.0V
0.8V
INPUT
OU TPUT
t
P LH
t
PH L
3V
0V
V
OH
1.5V
1.5V
V
O L
t
SK (p)
=
|t
P HL -
t
PL H
|
IN PU T
OU TPUT
Pulse
G enerator
R
T
D.U .T.
V
C C
V
IN
C
L
V
OUT
50pF
500
500
7.0V
t
PLH1
O UTPU T 1
O UTPU T 2
t
S K(o)
t
PLH2
3V
0V
V
O H
1.5V
1.5V
V
O L
V
O H
1.5V
V
O L
INPUT
t
P H L1
t
PH L2
t
SK (o)
t
SK (o)
=
|t
PLH2 -
t
P LH1
|
or
|t
P HL2 -
t
P HL1
|
INPUT
t
PD 1a
PAC KAG E 1 O UTPUT
PAC KAG E 2 O UTPUT
t
S K2(o)
t
P D2a
3V
0V
V
O H
1.5V
1.5V
V
OL
V
O H
1.5V
V
O L
t
P D 1b
t
P D2b
t
S K2(o)
t
SK(t)
= |t
PD2a -
t
P D1a
|
or
|t
PD 2b -
t
PD1b
|
TEST CIRCUITS AND WAVEFORMS
Package Delay
Pulse Skew - t
SK(P)
Enable and Disable Times
Output Skew (Same Bank) - t
SK1(O)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
Test Circuit for All Outputs
Package Skew - t
SK(T)
Output Skew (All Banks) - t
SK2(O)
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Test
Switch
Disable LOW
Closed
Enable LOW
Disable HIGH
GND
Enable HIGH
SWITCH POSITION
6
COMMERCIAL TEMPERATURE RANGE
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
XXX
Device Type
XX
Package
SO
PY
Q
810BT
810CT
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline IC
XX
Temp. Range
74
0
C to + 70C
Inverting, Non-Inverting Buffer/Clock Driver
IDT
FCT
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