INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
1
JANUARY 2002
IDT74FCT162260AT/CT/ET
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER
DESCRIPTION:
The FCT162260T Tri-Port Bus Exchangers are high-speed 12-bit latched
bus multiplexers/transceivers for use in high-speed microprocessor
applications. These Bus Exchangers support memory interleaving with latched
outputs on the B ports and address multiplexing with latched inputs on the B ports.
The Tri-Port Bus Exchanger has three 12-bit ports. Data may be transferred
between the A port and either/both of the B ports. The latch enable (LE1B, LE2B,
LEA1B and LEA2B) inputs control data storage. When a latch-enable input is
high, the latch is transparent. When a latch-enable input is low, the data at the
input is latched and remains latched until the latch enable input is returned high.
Independent output enables (OE1B and OE2B) allow reading from one port
while writing to the other port.
The FCT162260T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
times reducing the need for external series terminating resistors.
A-1B
LATCH
LEA1B
LE1B
LE2B
12
M
U
X
12
OE1B
12
A
1:12
1B-A
LATCH
1B
1:12
12
12
12
2B-A
LATCH
12
12
A-2B
LATCH
LEA2B
12
2B
1:12
OE2B
OEA
SEL
1
0
29
30
2
28
1
27
55
56
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5430/1
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
1A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V 10%
Balanced Output Drivers (24mA)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25C
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
INDUSTRIAL TEMPERATURE RANGE
2
IDT74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
OEA
LE1B
GN D
2B
2
V
CC
A
3
A
6
A
7
GN D
A
12
2B
3
2B
1
A
1
A
2
GN D
A
4
A
5
A
8
A
9
A
10
V
CC
1B
1
A
11
1B
2
LEA2B
2B
4
GN D
2B
5
2B
6
V
CC
2B
7
2B
8
GN D
2B
10
2B
11
2B
12
1B
11
1B
10
GN D
1B
9
V
CC
1B
6
1B
8
2B
9
1B
12
1B
7
1B
5
OE2B
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48
47
41
42
43
44
45
46
40
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
LE2B
GN D
SEL
1B
3
OE1B
GN D
1B
4
LEA1B
49
56
55
50
51
52
53
54
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
(1)
(1)
(1)
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals terminals for FCT162XXX.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
3.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
3.5
8
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
3
Signal
I/O
Description
A
(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
1B
(1:12)
I/O
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
2B
(1:12)
I/O
Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.
LEA1B
I
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LEA1B.
LEA2B
I
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on the HIGH to LOW
transition of LEA2B.
LE1B
I
Latch Enable Input for 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B-Port is latched on the HIGH to LOW
transition of LE1B
LE2B
I
Latch Enable Input for 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the A-Port is latched on the HIGH to LOW
transition of LE2B.
SEL
I
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data
transfer from 2B Port to A Port.
OEA
I
Output Enable for A Port (Active LOW).
OE1B
I
Output Enable for 1B Port (Active LOW).
OE2B
I
Output Enable for 2B Port (Active LOW).
PIN DESCRIPTION
FUNCTION TABLES
(1)
(1)
(1)
(1)
(1)
Inputs
Output
1B
2B
SEL
LE1B
LE2B
OEA
A
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
A
(1)
X
H
L
X
H
L
H
X
L
L
X
H
L
L
X
X
L
X
L
L
A
(1)
X
X
X
X
X
H
Z
Inputs
Outputs
A
LEA1B
LEA2B
OE1B
OE2B
1B
2B
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
B
(1)
L
H
L
L
L
L
B
(1)
H
L
H
L
L
B
(1)
H
L
L
H
L
L
B
(1)
L
X
L
L
L
L
B
(1)
B
(1)
X
X
X
H
H
Z
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
NOTES:
1. Output level before the indicated steady-state input conditions were established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
INDUSTRIAL TEMPERATURE RANGE
4
IDT74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current (Input pins)
(5)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Input HIGH Current (I/O pins)
(5)
--
--
1
I
IL
Input LOW Current (Input pins)
(5)
V
CC
= Max.
V
I
= GND
--
--
1
A
Input LOW Current (I/O pins)
(5)
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
250
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= Max.
--
5
500
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V
,
V
IN =
V
IH
or
V
IL,
V
O
= 1.5V
(3)
60
115
200
mA
I
ODH
Output HIGH Current
V
CC
= 5V
,
V
IN =
V
IH
or
V
IL,
V
O
= 1.5V
(3)
60
115
200
mA
V
OH
Output HIGH Voltage
V
CC
= Min
I
OH
= 24mA
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min
I
OH
= 24mA
--
0.3
0.55
V
V
IN
= V
IH
or V
IL
OUTPUT DRIVE CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is 5A at T
A
= 55C.
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
5
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
1.5
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
= V
CC
--
60
100
A/
Current
(4)
Outputs Open
V
IN
= GND
MHz
One Output Port Enabled
LExx = V
CC
One Input Bit Togging
One Output Bit Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
0.6
1.5
mA
Outputs Open
V
IN
= GND
fi = 10MHz
50% Duty Cycle
V
IN
= 3.4V
--
0.9
2.3
One Output Port Enabled
V
IN
= GND
LExx = V
CC
One Input Bit Togging
One Output Bit Toggling
V
CC
= Max.
V
IN
= V
CC
--
1.8
3.5
(5)
Outputs Open
V
IN
= GND
fi = 2.5MHz
50% Duty Cycle
One Output Port Enabled
V
IN
= 3.4V
--
4.8
12.5
(5)
LExx = V
CC
V
IN
= GND
Twelve Input Bit Togging
Twelve Output Bit Toggling
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
fi = Input Frequency
Ni = Number of Inputs at fi
INDUSTRIAL TEMPERATURE RANGE
6
IDT74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
FCT162260AT
FCT162260CT
FCT162260ET
Symbol Parameter
Condition
(1)
Min.
(2)
Max
Min.
(2)
Max
Min.
(2)
Max
Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
5.2
1.5
4.7
1.5
3.6
ns
t
PHL
Ax to 1Bx or Ax to 2Bx
R
L
= 500
t
PLH
Propagation Delay
1.5
5.6
1.5
5
1.5
3.6
ns
t
PHL
1Bx to Ax or 2Bx to Ax
t
PLH
Propagation Delay
1.5
5.2
1.5
4.7
1.5
4
ns
t
PHL
LExB to Ax
t
PLH
Propagation Delay
1.5
4.7
1.5
4.4
1.5
4
ns
t
PHL
LEA1B to 1Bx or LEA2B to 2Bx
t
PLH
Propagation Delay
1.5
5.2
1.5
4.7
1.5
4
ns
t
PHL
SEL to Ax
t
PZH
Output Enable Time
1.5
5.7
1.5
5.1
1.5
4.4
ns
t
PZL
OEA to Ax, OE1B or 1BX, or OE2B to 2Bx
t
PHZ
Output Disable Time
1.5
4.4
1.5
4
1.5
4
ns
t
PLZ
OEA to Ax, OE1B or 1BX, or OE2B to 2Bx
t
SU
Set-Up Time, HIGH or LOW Data to Latch
1.5
--
1
--
1
--
ns
t
H
Hold Time, Latch to Data
1
--
1
--
1
--
ns
t
W
Pulse Width, Latch HIGH
(4)
3
--
3
--
3
--
ns
t
SK(o)
Output Skew
(3)
--
0.5
--
0.5
--
0.5
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
7
Pulse
G enerator
R
T
D.U.T.
V
CC
V
IN
C
L
V
O UT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHR ONO US C O NTRO L
PRESET
CLEAR
ETC.
SYNCHRO NO US CO NTRO L
t
SU
t
H
t
RE M
t
SU
t
H
PRESET
CLEAR
CLO CK ENABLE
ETC.
HIGH-LOW -HIG H
PULSE
LO W -HIG H-LO W
PULSE
t
W
1.5V
1.5V
SAM E PHASE
INPUT TRANSITIO N
3V
1.5V
0V
1.5V
V
OH
t
PLH
O UTPUT
O PPO SITE PHASE
INPUT TRANSITIO N
3V
1.5V
0V
t
PLH
t
PH L
t
PH L
V
OL
CONTRO L
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NO RMALLY
LO W
OUTPUT
NO RMALLY
HIG H
SW ITCH
CLOSED
SW ITCH
O PEN
V
O L
0.3V
0.3V
t
PLZ
t
PZL
t
P ZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
O H
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
INDUSTRIAL TEMPERATURE RANGE
8
IDT74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
ORDERING INFORMATION
IDT X X
Tem p. Range
XX XX
Device Type
XX
Package
12-Bit Tri-Port Bus Exchanger
74
40
C to +85
C
162
Double-Density, 5 Volt, Balanced Drive
260AT
260CT
260ET
PV
PA
Shrink Sm all Outline P ackage
Thin Shrink Sm all Outline Package
FCT
XX X
Fam ily
DATA SHEET DOCUMENT HISTORY
1/18/2002
Removed Military temp grade
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
PDF 
ZIP